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http://dx.doi.org/10.6109/jkiice.2012.16.3.571

Efficient Design Methodology based on Hybrid Logic Synthesis for SoC  

Seo, Young-Ho (광운대학교)
Kim, Dong-Wook (광운대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.3, 2012 , pp. 571-578 More about this Journal
Abstract
In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.
Keywords
logic synthesis; SoC; chip; optimization; CTS; constraint; top-down; bottom-up;
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