• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.186-194
• /
• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Convergence Security Journal
• /
• v.15 no.2
• /
• pp.81-89
• /
• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.5 no.1
• /
• pp.52-58
• /
• 2005

We have developed a Group Method of Data Handling (GMDH) type algorithm for designing multi-layered neural networks. The algorithm is general enough that it will accept any number of inputs and any sized training set. Each neuron of the resulting network is a function of two of the inputs to the layer. The equation for each of the neurons is a quadratic polynomial. Several forms of the equation are tested for each neuron to make sure that only the best equation of two inputs is kept. All possible combinations of two inputs to each layer are also tested. By carefully testing each resulting neuron, we have developed an algorithm to keep only the best neurons at each level. The algorithm's goal is to create as accurate a network as possible while minimizing the size of the network. Software was developed to train and simulate networks using our algorithm. Several applications were modeled using our software, and the result was that our algorithm succeeded in developing small, accurate, multi-layer networks.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.115-126
• /
• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.2 no.1
• /
• pp.9-14
• /
• 2002

Boolean retrieval is simple and elegant. However, since there is no provision for term weighting, no ranking of the answer set is generated. As a result, the size of the output might be too large or too small. Relevance feedback is the most popular query reformulation strategy. in a relevance feedback cycle, the user is presented with a list of the retrieved documents and, after examining them, marks those which are relevant. In practice, only the top 10(or 20) ranked documents need to be examined. The main idea consists of selecting important terms, or expressions, attached to the documents that have been identified as relevant by the user, and of enhancing the importance of these terms in a new query formulation. The expected effect is that the new query will be moved towards the relevant documents and away from the non-relevant ones. Local analysis techniques are interesting because they take advantage of the local context provided with the query. In this regard, they seem more appropriate than global analysis techniques. In a local strategy, the documents retrieved for a given query q are examined at query time to determine terms for query expansion. This is similar to a relevance feedback cycle but might be done without assistance from the user.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.67-74
• /
• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.2
• /
• pp.85-90
• /
• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.4
• /
• pp.221-228
• /
• 2007

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

• Proceedings of the KIPE Conference
• /
• 2010.07a
• /
• pp.107-108
• /
• 2010

Uncertainty and insecurity is a serious issue in all aspects of our society today as the change in environmental and societal conditions became more apparent than ever before through various disasters. Thus, it is now an important point in time for the government and responsible firms to implement an innovative scientific disaster management method that can lead to establishing a more secure and stable future. Therefore, authors have developed ubiquitous- based disaster prevention automation system(DPAS). The system would follow up after sensors detecting fires, thefts, torrents, floods, and infrastructural leaks. It prevents disasters in advance by utilizing a wireless communications net or ethernet to conduct real-time monitoring from a remote place. The system also has an advantage as it is designed in a compact size that applies a precision-focused programmable logic controller(PLC) of one-chip type.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.9 no.1
• /
• pp.10-15
• /
• 2009

With the development of techniques, robots are getting smaller, and the number of robots needed for application is greater and greater. How to coordinate large number of autonomous robots through local interactions has becoming an important research issue in robot community. Swarm Robot Systems (SRS) is a system that independent autonomous robots in the restricted environments infer their status from pre-assigned conditions and operate their jobs through the cooperation with each other. In the SRS, a robot contains sensor part to percept the situation around them, communication part to exchange information, and actuator part to do a work. Especially, in order to cooperate with other robots, communicating with other robots is one of the essential elements. Because Bluetooth has many advantages such as low power consumption, small size module package, and various standard protocols, it is rated as one of the efficient communicating technologies which can apply to small-sized robot system. In this paper, we will develop Bluetooth communicating system for autonomous robots. And we will discuss how to construct and what kind of procedure to develop the communicating system for group behavior of the SRS under intelligent space.