• 한국표면공학회지
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• 제33권2호
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• International Journal of Reliability and Applications
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• 제13권2호
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• pp.91-104
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• 2012

Sarhan and Kundu (2009) introduced a new distribution named as the generalized linear failure rate distribution. This distribution generalizes several well known distributions. The probability density function of the generalized linear failure rate distribution can be right skewed or unimodal and its hazard function can be increasing, decreasing or bathtub shaped. This distribution can be used quite effectively to analyze lifetime data in place of linear failure rate, generalized exponential and generalized Rayleigh distributions. In this paper, we apply the simulated annealing algorithm to obtain the maximum likelihood point estimates of the parameters of the generalized linear failure rate distribution. Simulated annealing algorithm can not only find the global optimum; it is also less likely to fail because it is a very robust algorithm. The estimators obtained using simulated annealing algorithm have been compared with the corresponding traditional maximum likelihood estimators for their risks.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 한국재료학회지
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• 제12권10호
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• 국제학술발표논문집
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• The 2th International Conference on Construction Engineering and Project Management
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• pp.530-539
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• 2007

Many construction projects such as highways, pipelines, tunnels, and high-rise buildings typically contain repetitive activities. Research has shown that the Critical Path Method (CPM) is not efficient in scheduling linear construction projects that involve repetitive tasks. Linear Scheduling Method (LSM) is one of the techniques that have been developed since 1960s to handle projects with repetitive characteristics. Although LSM has been regarded as a technique that provides significant advantages over CPM in linear construction projects, it has been mainly viewed as a graphical complement to the CPM. Studies of scheduling linear construction projects with resource consideration are rare, especially with multiple resource constraints. The objective of this proposed research is to explore a resource assignment mechanism, which assigns multiple critical resources to all activities to minimize the project duration while satisfying the activities precedence relationship and resource limitations. Resources assigned to an activity are allowed to vary within a range at different stations, which is a combinatorial optimization problem in nature. A heuristic multiple resource allocation algorithm is explored to obtain a feasible initial solution. The Simulated Annealing search algorithm is then utilized to improve the initial solution for obtaining near-optimum solutions. A housing example is studied to demonstrate the resource assignment mechanism.

• 한국자기학회지
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• 제11권2호
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• pp.78-83
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• 2001

The thermal characteristics of TMR devices by using Fast Linear Annealing method has been studied. A computer program that employs the finite differential method has been developed to simulate the temperature distribution of a diameter of 4" silicon wafer, which is subjected to radiation heat from the halogen lamp. We adopted the temperature of 350$\^{C}$, which is the highest temperature usually used in annealing for magnetic thin films. We changed moving velocity of the lamp from 0.05 mm/sec to 1 mm/sec. The moving velocity of halogen lamp has less effect on the local peak temperature of the sample only about 40$\^{C}$. Therefore, we may be able to anneal TMR devices in such short time of 1 minute and 40 seconds per one wafer, using the Fast Linear Annealing method.

• 한국재료학회지
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• 제14권5호
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 한국재료학회지
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• 제10권10호
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• pp.665-670
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• 2000

실온에서 직접 접합된 실리콘 기판의 접합강도를 향상기키기 위하여 기존의 고온 로내 열처리법을 대체할 수 있는 선형 열처리법을 개발하였다. 한 개의 열원과 타원형 반사경으로 구성된 선형 열처리법은 접합면의 간격이 열처리 온도의 증가와 더불어 감소하는 특성과 온도 증가와 더불어 접합면에 생성된는 기체상의 밀도가 증가하는 현상을 응용하여 접합면의 기체상을 밀도차이를 이용하여 기판 외부로 방출시키는 방법으로 Si$\mid$$\mid$Si 기판쌍 및 Si$\mid$$\mid$$SiO_2/Si$ 기판쌍의 직접 접합에 적용하여 보았다. IR camera와 HRTEM으로 직접 관찰한 접합면은 실온에서 접합면에 침투한 외부 불순물에 의한 비접합 영역을 제외하고는 자제 생성된 기체상에 의한 비접합 영역은 나타나지 않았고 매우 깨끗한 접합계면을 나타내었다. 접합된 기판쌍을 Crack opening법과 인장시험법을 적용하여 접합 강도를 측정하였다. 접합 강도는 열처리 온도의 증가와 더불어 점차로 증가하였고 두 측정방법 모두 동일한 경향성을 나타내었다.

• 방사성폐기물학회지
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• 제4권3호
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• pp.209-216
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• 2006

중성자가 조사된 흑연에 내재되어 있는 Wigner 에너지를 배출시키는 방법의 하나인 가열냉각공정의 적용 예로 DSC(미분 주사선 열량계) 측정을 통해 흑연으로부터 Wigner 에너지가 배출되는 열 배출 특성을 연구하였다. 일정온도 상승 방법 에 의한 DSC 운전에서 중성자가 조사된 흑연을 가열냉각(annealing)하는 동안 배출되는 Wigner 에너지의 총량과 처리온도에 따른 배출속도를 측정하였다. 연구로 2호기(KRR-2) thermal column 내에 위치별로 중성자의 조사량에 차이가 나는 흑연 시료를 분말로 만들어 상온에서 $500^{\circ}C$까지의 온도 범위에서 DSC를 운전하고 이로부터 Wigner 에너지의 배출 속도를 측정하였다. 가열냉각 동안 중성자가 조사된 흑연에서 배출되는 Wigner 에너지의 배출 특성은 가변적 활성화 에너지 속도 식으로 잘 상관시킬 수 있었다.