• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.149-151
• /
• 2002

We had been developing the variety of parallel processing systems in order to improve the processing speed of visual media applications. These systems were using multi-access memory system(MAMS) as a parallel memory system, which provides the capability of the simultaneous accesses of image points in a line-segment with an arbitrary degree, which is required in many low-level image processing operations such as edge or line detection in a particular direction, and so on. But, the performance of these systems did not give a faithful speed because of asynchronous feature between MAMS and processing elements. To improve the processing speed of these systems, we have been investigated a pipelined parallel processing system using MAMS. Although the system is considered as being the single instruction multiple data(SIMD) type like the early developed systems, the performance of the system yielded about 2.5 times faster speed.

• ETRI Journal
• /
• 제25권5호
• /
• pp.288-296
• /
• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.647-648
• /
• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Structural Engineering and Mechanics
• /
• 제82권5호
• /
• pp.571-585
• /
• 2022

As a vital component of power grids, long-span transmission tower-line systems are vulnerable to wind load excitation due to their high flexibility and low structural damping. Therefore, it is essential to reduce wind-induced responses of tower-line coupling systems to ensure their safe and reliable operation. To this end, a shape memory alloy-bidirectional tuned mass damper (SMA-BTMD) is proposed in this study to reduce wind-induced vibrations of long-span transmission tower-line systems. A 1220 m Songhua River long-span transmission system is selected as the primary structure and modeled using ANSYS software. The vibration suppression performance of an optimized SMA-BTMD attached to the transmission tower is evaluated and compared with the effects of a conventional bidirectional tuned mass damper. Furthermore, the impacts of frequency ratios and SMA composition on the vibration reduction performance of the SMA-BTMD are evaluated. The results show that the SMA-BTMD provides superior vibration control of the long-span transmission tower-line system. In addition, changes in frequency ratios and SMA composition have a substantial impact on the vibration suppression effects of the SMA-BTMD. This research can provide a reference for the practical engineering application of the SMA-BTMD developed in this study.

• Journal of Information Processing Systems
• /
• 제14권2호
• /
• pp.499-509
• /
• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• 동의신경정신과학회지
• /
• 제19권3호
• /
• pp.55-68
• /
• 2008

Background: Microglia produces a barrage of factors (IL-l, TNF-$\alpha$, NO, superoxide) that are toxic to neurons and playa major role in the cellular immune response associated with the pathology of Alzheimer's disease(AD). OJaJiHwangEumJa(OJJHEJ) has been usually used for the treatment of senile disorders. For enhancing efficacy and convenience, the change of the drug delivery device of oriental herbal medicine is required. Objective: This experiment was designed to investigate the effect of the OJJHEJ hot water extract & ultra-fine powder on proinflammatory cytokine of microglia and memory deficit model. Method: The effects of the OJJHEJ hot water extract on production of IL-1$\beta$, IL-6, TNF-$\alpha$, in BV2 microglial cell line treated by lipopolysacchaide(LPS) were investigated. The effects of the OJJHEJ hot water extract & ultra-fine powder on the behavior of the memory deficit mice induced by scopolamine and AChE in serum of the memory deficit mice induced by scopolamine were investigated. Results: 1. The OJJHEJ hot water extract suppressed the production of IL-1$\beta$, IL-6, TNF-$\alpha$ in BV2 microglial cell line and the production of IL-6 was suppressed significantly. 2. The OJJHEJ hot water extract & ultra-fine powder decreased AChE significantly in the serum of the memory deficit mice induced by scopolamine. 3. The OJJHEJ hot water extract & ultra-fine powder groups showed significantly inhibitory effect on the scopolamine-induced impairment of memory in the experiment of Morris water maze. Conclusions: This experiment shows that the OJJHEJ hot water extract & ultra-fine powder might be effective for the prevention and treatment of memory impairment diseases. Investigation into the clinical use of the OJJHEJ hot water extract & ultra-fine powder for Alzheimer's disease is suggested for future research.

• Journal of Information Display
• /
• 제9권1호
• /
• pp.6-13
• /
• 2008

Mobile phones use the embedded memory in LDI (LCD Driver IC). In memory accessing mode, data overlapping phenomenon can occur. These days, various contents such as DMB, Camera, Game are merged to phone. Accordingly, with more data transmission, there would be more data overlapping phenomenon in memory accessing mode. Human eyes perceive this data overlapping phenomenon as simply horizontal line noise. The cause of the data overlapping phenomenon was analysed in this paper. The data overlapping phenomenon can be changed by the speed of data transmission between the host and LDI. The optimum memory accessing position can be defined. This paper proposes a new algorithm for avoiding data overlapping.

• IMMUNE NETWORK
• /
• 제23권1호
• /
• pp.11.1-11.11
• /
• 2023

Memory T cells that mediate fast and effective protection against reinfections are usually generated upon recognition on foreign Ags. However, a "memory-like" T-cell population, termed virtual memory T (T_VM) cells that acquire a memory phenotype in the absence of foreign Ag, has been reported. Although, like innate cells, T_VM cells reportedly play a role in first-line defense to bacterial or viral infections, their protective or pathological roles in immune-related diseases are largely unknown. In this review, we discuss the current understanding of T_VM cells, focusing on their distinct characteristics, immunological properties, and roles in various immune-related diseases, such as infections and cancers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권1호
• /
• pp.20-30
• /
• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• 대한전자공학회논문지SD
• /
• 제41권10호
• /
• pp.105-113
• /
• 2004

본 논문은 B-I (delay insensitive) 모델을 사용하는 비동기 프로세서의 메모리 동작 완료 신호 생성 회로를 제안한다. 제안된 설계 방법은 더미셀과 완료 신호 생성 회로를 이용하여 메모리의 읽기 및 쓰기 동작의 완료 신호를 생성한다. 비트라인과 메모리 셀의 지연을 고려하여 메모리를 지수적 블록 크기로 나누어 최소의 완료 신호 회로를 추가하여 D-I 모델로 동작하는 메모리를 설계하였다. 각 구역의 크기가 지수적으로 증가하도록 메모리를 분할하는 제안된 분할 알고리즘은 기존의 동일한 크기를 갖는 구역들로 메모리를 분할하는 방법에 비해 약 40% 정도 동작 지연을 개선하였다.