• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.190-193
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• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1154-1157
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• 2006

Organic thin-film transistors (OTFTs) based on a semiconducting polymer have been fabricated using an organic patterning methodology. Laser assisted lift-off (LALO) technique, ablating selectively the hydrophobic layer by an excimer laser, was used for producing a semiconducting polymer channel in the OTFT with high resolution. The selective wettability of a semiconducting polymer, poly (9-9-dioctylfluorene-co-bithiophene) (F8T2), dissolved in a polar solvent was found to define precisely the pattering resolution of the active channel. It is demonstrated that in the F8T2 TFTs fabricated using the LALO technique and is applicable for the larger area display.

• Proceedings of the Materials Research Society of Korea Conference
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• 2008.11a
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• pp.24.2-24.2
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• 2008

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.1
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• pp.21-26
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• 2021

Single-layer graphene is grown directly on Ti-buffered SiO2 at 100℃. As a result of the AFM measurement of the Ti buffer layer, the roughness of approximately 0.2 nm has been improved. Moreover, the Raman measurement of graphene grown on it shows that the D/G intensity ratio is extremely small, approximately 0.01, and there are no defects. In addition, the 2D/G intensity ratio had a value of approximately 2.1 for single-layer graphene. The sheet resistance is also 89 Ω/□, demonstrating excellent characteristics. The problem was solved by using graphene and a lift-off patterning method. Low-temperature direct-grown graphene does not deteriorate after the patterning process and can be used for device and micro-patterning research.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.294-302
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• 2007

We studied on possibility of the application of photolithography technique to patterning the organic active layer poly(3-hexylthiophene) (P3HT). In the case of selective etching method, we made thin oxide film on P3HT thin film using $O_2$ treatment. We achieved the field-effect mobilities in the saturation regime ${\sim}1.2{\times}10^{-3}\;cm^2/V{\cdot}s$, $I_{on/off}$ ratios ${\sim}10^5$ in the selective etching method, ${\sim}7.4{\times}10^{-4}cm^2/V{\cdot}s$, $I_{on/off}$ ratios ${\sim}5{\times}10^3$ in the lift-off one. These values are higher than ones of the unpatterned P3HT-based OTFTs. On the basis of the above results, we demonstrate the photolithographic patterning for P3HT active layer is successfully carried out without degradation of P3HT.

• ETRI Journal
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• v.29 no.6
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• pp.814-816
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• 2007

Conventional lithography methods of gold patterning are based on deposition and lift-off or deposition and etching. In this letter, we demonstrate a novel method of gold patterning using spin-coatable gold electron-beam resist which is functionalized gold nanocrystals with amine ligands. Amine-stabilized gold electron beam resist exhibits good sensitivity, 3.0 mC/$cm^2$, compared to that of thiol-stabilized gold electron beam resists. The proposed method reduces the number of processing steps and provides greater freedom in the patterning of complex nanostructures.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.28.2-28.2
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• 2009

Cobalt thin film was fabricated by a novel NH3-based plasma-enhanced atomic layer deposition(PE-ALD) using Co(CpAMD) precursor and $NH_3$ plasma. The PE-ALD Co thin films were produced well on both thermally grown oxide (100 nm) $SiO_2$ and Si(001) substrates. Chemical bonding states and compositions of PE-ALD Co films were analyzed by XPS and discussed in terms of resistivity and impurity level. Especially, we successfully developed PE-ALD Code position at very low growth temperature condition as low as $T_s=100^{\circ}C$, which enabled the fabrication of Co patterns through lift-off method after the deposition on PR patterned substrate without any thermal degradation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1489-1492
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• 2005

Compared to other nano-patterning techniques, Nano imprint Lithography (NIL) has some advantages of high throughput and low process cost. To imprint low temperature and pressure, UV Nano imprint Lithography, which using the monomer based UV curable resin is suggested. Because fabrication of high fidelity pattern on topographical substrate is difficult, bi-layer Nano imprint lithography, which are consist of easily removable under-layer and imprinted pattern, is being used. If residual layer is not remained after imprinting, and under-layer is removed by oxygen RIE etching, we might be able to fabricate the bi-layer pattern for easy lift-off process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.36-40
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• 2018

We have developed a nonlithographic patterning technique using polystyrene nanoparticles to form nanonet channel structures which is promising for high-performance TFT applications. Nanoparticles assisted patterning (NAP) is a technique to form uniform nano-patterns by applying lift-off and dry etch process. Oxygen plasma treatment was used to control the diameters of nanonet hole size to realize a branch width down to 100 nm. NAP technology can be very promising to fabricate nanonet structure with advantages of lower manufacturing cost and large-area patterning capability.