• Journal of Power Electronics
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• v.16 no.1
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• pp.133-141
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• 2016

This paper focuses on the development of a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) based on the main circuit of dual buck inverters. This topology has been described as not having any shoot-through problems, no body-diode reverse recovery problems and the half-cycle work mode found in the traditional Multi-Level Flying-Capacitor Inverter (MLFCI). It has been shown that the flying-capacitor voltages of this inverter can be regulated by the redundant state selection within one pole. The voltage balance of the flying-capacitors can be achieved by charging or discharging in the positive (negative) half cycles by choosing the proper logical algorithms. This system has a simple structure but demonstrates improved performance and reliability. The validity of this inverter is conformed through computer-aided simulation and experimental investigations.

• Journal of IKEEE
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• v.26 no.2
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• pp.271-279
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• 2022

This paper proposes an advanced dead-time compensation method for dual inverter with a floating capacitor. The dual inverter with floating capacitor is composed of double two-level inverters and a bulk electrolytic capacitor. The output voltage of the dual inverter is dropped by the conduction voltage of the power semiconductors. The voltage drop and dead-time cause the fundamental and harmonic distortions of output currents. When supplied power for OEW-load is low, the dual inverter operates as single inverter for effective operation. The dead-time compensation method for the dual inverter operated as single inverter is needed for reliability. The proposed method using band pass filter in this paper compensates dead-time, dead-time error and changed voltage drop error of power semiconductors for the dual inverter and dual inverter operated as single inverter. The effectiveness of the proposed method is verified by simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• Journal of Power Electronics
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• v.15 no.4
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• pp.910-919
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• 2015

The use of a PV grid-connected inverter with non-isolated topology and without a transformer is good for improving conversion efficiency; however, this inverter has become increasingly complicated for eliminating leakage current. To simplify the complicated architecture of traditional three-level dual buck inverters, a new dual Buck three-level PV grid-connected inverter topology is proposed. In the proposed topology, the voltage on the grounding stray capacitor is clamped by large input capacitors and is equal to half of the bus voltage; thus, leakage current can be eliminated. Unlike in the traditional topology, the current in the proposed topology passes through few elements and does not flow through the body diodes of MOSFET switches, resulting in increased efficiency. Additionally, a multi-loop control method that includes voltage-balancing control is proposed and analyzed. Both simulation and experimental results are demonstrated to verify the proposed structure and control method.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1500-1511
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• 2017

The purpose of this paper is to study a high-performance control scheme for neutral-point-clamping three-level (NPC-3L) inverter fed dual three-phase permanent magnet synchronous motor (PMSM) drives by considering some asymmetric factors such as the non-identical parameters in phase windings. To implement this, the system model is analyzed for dual three-phase PMSM drives with asymmetric factors based on the vector space decomposition (VSD) principle. Based on the equivalent circuits, PI controllers with feedforward compensation are used in the d-q subspace for regulating torque, where the cut-off frequency of the PI controllers are set at the twice the fundamental frequency for compensating both the additional DC component and the second order component caused by asymmetry. Meanwhile, proportional resonant (PR) controllers are proposed in the x-y subspace for suppressing the possible unbalanced currents in the phase windings. A dual three-phase space vector modulation (DT-SVM) is designed for the drive, and the balancing factor is designed based on the numerical fitting surface for balancing the DC link capacitor voltages. Experimental results are given to demonstrate the validity of the theoretical analysis and the proposed control scheme.

• Journal of Power Electronics
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• v.17 no.1
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• pp.67-75
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• 2017

Due to the excessive zero-sequence voltage in dual three-level inverter fed open-end winding induction motor systems, zero-sequence circumfluence which is harmful to switching devices and insulation is then formed when operating in a single DC voltage source supplying mode. Traditionally, it is the mean value instead of instantaneous value of the zero-sequence voltage that is eliminated, through adjusting the durations of the operating vectors. A new strategy is proposed for zero-sequence voltage elimination, which utilizes unified voltage modulation and a decoupled SVPWM strategy to achieve two same-sized equivalent vectors for an angle of $120^{\circ}$, generated by two inverters independently. Both simulation and experimental results have verified its efficiency in the instantaneous value elimination of zero-sequence voltage.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1421-1428
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• 2015

The efficiency and reliability of the dual-buck inverter (DBI) were greatly improved by eliminating the shoot-through problem and optimally designing the freewheeling diode. The traditional DBI suffers from large harmonic components with low output voltage and large capacity output filter inductor. To overcome the aforementioned disadvantages, a modified DBI (MBDI) was proposed by adopting a quasi-resonant link and pulse density modulation (PDM). This paper first introduces the working principle of the MBDI and PDM, and then the selection principle of system parameters is presented. Finally, a mathematical model of the MBDIis built, and an experiment prototype is set up. Simulation and experimental results verify the correctness of the theoretical analysis and the feasibility of the scheme.

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1403-1412
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• 2019

A coupled inductor-dual boost-inverter (CIDBI) with a differential structure has been presented for application to a micro-inverter photovoltaic module system due to its turn ratio of a high-voltage level. However, it is difficult to design a CIDBI converter with a conventional PI regulator to be stable and achieve good dynamic performance, given the fact that it is a high order system. In view of this situation, a sliding mode control (SMC) strategy is introduced in this paper, and two different sliding mode controllers (SMCs) are proposed and adopted in the left and right side of two Boost sub-circuits to implement the corresponding regulation of the voltage and current. The schemes of the SMCs have been elaborated in this paper including the establishment of a system variable structure model, selection of the sliding surface, determination of the control law, and presentation of the reaching conditions and sliding domain. Finally, the mathematic analysis and the proposed SMC are verified by experimental results.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.262-264
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• 1996

This paper presents a new dual loop control using novel vector phase locked loop(VP-PLL) for a high power static var compensator(SVC) with three-level GTO voltage source inverter(VSI). Through circuit DQ-transformation, a simple dq-axis equivalent circuit is obtained. From this, DC analysis is carried out to obtain maximum controllable phase angle ${\alpha}_{max}$ per unit current between the three phase source and the switching function of inverter, and AC open-loop transfer function is given. Because ${\alpha}_{max}$ becomes small in high power SVC, this paper proposes VP-PLL for more accurate $\alpha$-control. As a result, the overall control loop has dual loop structure, which consists of inner VP-PLL for synchronizing the phase angle with source and outer Q-loop for compensating reactive power of load. Finally, the validity of the proposed control method is verified through the experimental results.