1 |
F. Z. Peng, “A generalized multilevel inverter topology with self voltage balancing,” IEEE Trans. Ind. Appl., Vol. 37, No. 2, pp. 611-618, Mar./Apr. 2001.
DOI
|
2 |
J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 724-738, Aug. 2002.
DOI
|
3 |
F. Khoucha, S. M. Lagoun, K. Marouani, A. Kheloui, and M. E. H. Benbouzid, “Hybrid cascaded H-bridge multilevel-inverter induction-motor-drive direct torque control for automotive applications,” IEEE Trans. Ind. Electron., Vol. 57, No. 3, pp. 892-899, Mar. 2010.
DOI
|
4 |
X. M. Yuan and I. Barbi, “Fundamentals of a new diode clamping multilevel inverter,” IEEE Trans. Power Electron., Vol. 15, No.4, pp. 711-718, Jul. 2000.
DOI
|
5 |
C. Cecati, F. Ciancetta, and P. Siano, “A multilevel inverter for photovoltaic systems with fuzzy logic control,” IEEE Trans. Ind. Electron., Vol. 57, No. 12, pp. 4115-4125, Dec. 2010.
DOI
|
6 |
M. F. Escalante, J. C. Vannier, and A. Arzande, “Flying capacitor multilevel inverters and DTC motor drive applications,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 809-815, Aug. 2002.
DOI
|
7 |
P. W. Sun, C. Liu, J. S. Lai, and C. L. Chen, “Cascade dual buck inverter with phase-shift control,” IEEE Trans. Power Electron., Vol. 27, No. 4, pp. 2067-2077, Apr. 2012.
DOI
|
8 |
W. Yang, F. Hong, and C. H. Wang, "A Novel Dual Buck Half Bridge Five-level Inverter," in Proc. the Chinese Society of Electrical Engineering, Vol. 31, No. 24, pp. 19-25, 2011.
|
9 |
M. B. Smida and F. B. Ammar, “Modeling and DBC-PSC-PWM control of a three-phase flying-capacitor stacked multilevel voltage source inverter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2231-2239, Jul. 2010.
DOI
|
10 |
S. Jin and Y. R. Zhong, "Novel three-level SVPWM algorithm considering neutral-point control and narrow-pulse elimination and dead-time compensation," in Proc. the Chinese Society of Electrical Engineering, Vol. 25, No. 6, pp. 60-66, Jun. 2005.
|
11 |
S. R. Minshull, C. M. Bingham, D. A. Stone, and M. P. Foster, “Compensation of Nonlinearities in Diode-clamped Multilevel Converters,” IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2651-2658, Aug. 2010.
DOI
|
12 |
D. L. Liu, R. B. Wu, and Y. Zhang, "Inverter dead time compensation of zero current clamping based on fuzzy control," in Transactions of China Electrotechnical Society, Vol. 26, No. 8, pp. 119-124, 2011.
|
13 |
B. B. Lazhar, “On the compensation of dead time and zero-current crossing for a PWM-inverter-controlled AC servo drive,” IEEE Trans. Ind. Electron., Vol. 51, No. 5, pp. 1113-1117, Oct. 2004.
DOI
|
14 |
D. S. Zhou and D. G. Rouaud, “Dead-time effect and compensations of three-level neutral point clamp inverters for high-performance drive applications,” IEEE Trans. Power Electron., Vol. 14, No. 4, pp. 782-788, Jul. 1999.
DOI
|
15 |
L. Liu and M. G. Deng, "A new approach of dead-time compensation for voltage-fed PWM inverter," in 2011International Conference on Electric Information and Control Engineering, pp. 1039-1042, Apr. 2011.
|
16 |
F. Gao, J. H. Yuan, D. Li, P. C. Loh, and H. L. Gao, "Dead-time elimination and zero common mode voltage operation of neutral-point-clamped inverter," in 8th International Conference on Power Electronics and ECCE Asia, pp.2880-2885, May/Jun. 2011.
|
17 |
G. L. Wang, D. G. Xu, and Y. Yuet, "A novel strategy of dead-time compensation for PWM voltage-source inverter," in 23rd Annual IEEE Applied Power Electronics Conference and Exposition, pp. 1779-1783, Feb. 2008.
|
18 |
M. Liu and F. Hong, "FPGA controlled dual buck half bridge three-level inverter," in Proc. the 2012 9th International Bhurban Conference on Applied Sciences &Technology (IBCA5T), pp: 83-86, Jan. 2012.
|
19 |
C. H. Zhu, F. H. Zhang, and Y. G. Yan, "A novel split phase dual buck half bridge inverter," in Applied Power Electronics Conference and Exposition, Vol. 2, pp. 845-849, Mar. 2005,.
|
20 |
M. Liu, F. Hong, and C. H. Wang, "Three-level dual buck inverter with coupled-inductance," in Asia-Pacific Power and Energy Engineering Conference, pp. 1-4, Mar. 2010.
|
21 |
F. Hong, R. Z. Shan, H. Z. Wang, and Y. G. Yan, "A novel dual buck inverter with integrated magnetic," in Transactions of China Electrotechnical Society, Vol. 22, No. 6, pp. 76-81, 2007.
|
22 |
P. Lezana, R. Aguilera, and D. E. Quevedo, “Model predictive control of an asymmetric flying capacitor converter,” IEEE Trans. Ind. Electron., Vol. 56, No. 6, pp. 1839-1846, Jun. 2009.
DOI
|
23 |
Z. L. Yao, L. Xiao, and Y. G. Yan, “Control strategy for series and parallel output dual-buck half bridge inverters based on DSP control,” IEEE Trans. Power Electron., Vol. 24, No. 2, pp. 434-444, Feb. 2009.
DOI
|
24 |
F. Hong, M. Liu, B. J. Ji, and C. H. Wang, "A Capacitor Voltage Buildup Method for Flying Capacitor Multilevel Inverters," in Proc. the Chinese Society of Electrical Engineering, Vol. 32, No.6, pp. 17-23, 2012.
|
25 |
A. Shukla, A. Ghosh, and A. Joshi, “Flying-capacitor-based chopper circuit for DC capacitor voltage balancing in diode-clamped multilevel inverter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2249-2261, Jul. 2010.
DOI
|
26 |
J. Liu and Y. G. Yan, “Novel current mode controlled bi-buck half bridge inverter,” Journal of Nanjing University of Aeronautics & Astronautics, Vol. 35, No. 2, pp. 122-126, 2003.
|