• 전기학회논문지
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• 제59권11호
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• pp.2108-2113
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• 2010

The Long Term Evolution (LTE) system is based on the Orthogonal Frequency Division Multiplexing (OFDM) and relies its channel estimation on the lattice-type pilot samples in the multipath fading channel environment. The estimation of the channel frequency response (CFR) makes use of the least squares estimate (LSE) for each pilot samples, followed by an interpolation both in time- and in frequency-domain to fill up the channel estimates for subcarriers corresponding to data samples. Any interpolation scheme could be adopted for this purpose. Depending on the requirements of the target system, we may choose a simple linear interpolation or a sophisticated one. For any choice of an interpolation scheme, these is a trade-off between estimation accuracy and numerical cost. For those wireless communication systems based on the OFDM and the preamble-type pilot structure, the DFT-based channel estimation and its variants have been successfully. Yet, it may not be suitable for the lattice-type pilot structure, since the pilot samples are not sufficient to provide an accurate estimate and it is known to be sensitive to the location as well as the length of the time-domain window. In this paper, we propose a simple interpolated based on the upsampling mechanism in the multirate signal processing. The proposed method provides an excellent alternative to the DFT-based methods in terms of numerical cost and accuracy. The performance of the proposed technique is verified on a multipath environment suggested on a 3GPP LTE specification.

• 대한전자공학회논문지SD
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• 제43권4호
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• pp.23-30
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• 2006

본 연구에서는 나노 스케일 MuGFET(Mutiple-Gate FETs)의 단채널 효과와 corner effect를 3차원 시뮬레이션을 통하여 분석하였다. 문턱전압 모델을 이용하여 게이트 숫자(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4)를 구하였으며 추출된 게이트 숫자를 이용하여 각각의 소자 구조에 맞는 natural length($\lambda$)값을 얻을 수 있었다. Natural length를 통하여 MuGFET의 단채널 효과를 피할 수 있는 최적의 소자 구조(실리콘 두께, 게이트 산화막의 두께 등)를 제시 하였다. 이러한 corner effect를 억제하기 위해서는 채널 불순물의 농도를 낮게 하고, 게이트 산화막의 두께를 얇게 하며, 코너 부분을 약 17%이상 라운딩을 해야 한다는 것을 알 수 있었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• 한국항해항만학회지
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• 제29권1호
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• pp.9-15
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• 2005

항만의 계획 및 개발단계에서 중요한 요소 중 하나는 항로의 설계이다. 대부분의 경우 수심이 확보되어 있는 수역이라면 항로의 설계의 핵심은 항로의 배치와 항로폭의 결정이 될 것이다. 본 연구에서는 가변범퍼영역모델을 이용하여 항로를 설계하고 평가한다 이 모델은 선박의 주요명세, 선박점용이론, 선박의 속력, 선박지휘자의 조선기술과 경험을 항로설계에 반영할 수 있으며, 특히 선박의 운동 및 조종특성에 영향을 주는 외력을 정확하게 반영할 수 있다. 이를 위해 선박조종자의 선박제어와 외력 등에 의해 생성되는 선박의 동적데이터를 분석하기 위해 전기능선박조종시뮬레이터를 이용하였으며, 항로의 적정성과 안전성을 평가하기 위해 점용도와 점용지수를 정의한다. 개발된 항로설계기법을 울산신항개발계획에 적용하였다. 이 계획에서 항로의 폭은 전장의 1.5배 중심교각 57도인 만곡부의 곡률반경은 전장의 5.0배로 설계하였으며, 항로부근에는 SBM이 위치하고 있다. 모델의 적용결과 항로의 폭과 곡률반경은 적절하지만, 대각도 변침과 항로부근에 위치한 SBM에 의해 선박조선상의 어려움이 야기되는 것으로 분석되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Journal of Advanced Marine Engineering and Technology
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• 제22권6호
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• pp.844-853
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• 1998

Natural and forced convection experiments were carried out in order to investigate the effects of channel spacing gap between protrusions and number of rows of protrusion, In natural convection the optimum channel spacing was found to be approximately 20mm regardless of the protrusion gaps. For optimum channel spacing the heat transfer coefficients were converged to an asymptotic value after the fourth row. The heat transfer coefficient for each row approaches to constant values for protrusion gaps larger than 10 mm. An experimental correlation has been suggested by using a modified Rayleigh number based on the dimensionless characteristic length(G/L). In forced convec-tion the heat transfer coefficients were not merged to an asymptote until the fifty row and increases as the channel spacing at the constant Reynolds number decreases.

• 전자공학회논문지A
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• 제33A권10호
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• 해양환경안전학회지
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• 제26권4호
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• pp.309-316
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• 2020

항만 진입항로 설계 시에는 선박 입출항에 따른 통항 안전성이 우선적으로 확보될 수 있도록 적정한 항로 폭이 고려되어야 한다. 통항 안전성에 요구되는 최소 항로 폭 산출은 선종별 선박의 크기와 운항 속력 등에 따라 상이하게 나타나는 조종성능을 포함한 선박 요소, 바람, 조류 및 파랑에 따른 환경적 요소, 그리고 운항자 개인별 경험과 판단력 등에 따른 인적 요소 및 해상교통량, 항해지원 시설 등의 기타 요소를 종합적으로 검토하여 결정해야 한다. 그러나, 우리나라 항로 폭 설계 기준이 국제수상교통시설협회나 미국, 일본 등의 기준과 비교할 때 단순히 선박 길이 요소만으로 산정하고 있어, 이에 대한 개선이 요구된다. 본 연구에서는 배속 선박조종시뮬레이션을 활용하여 다양한 형태의 선박 및 환경적 요소를 고려하여, 직선항로에서 일방통항에 요구되는 적정 항로 폭에 대한 평가를 실시하였다. 대표적인 연구 결과로 일반적인 운항 선속 10노트 기준 풍속 25노트의 바람과 유속 2노트의 조류, 파고 약 3 m의 파랑이 작용할 경우, 15만 GT급 크루즈선은 선박 길이(L) 대비 0.67~0.91, 1만 2천 TEU급 컨테이너선은 0.79~1.17, 30만 DWT급 원유운반선은 1.02~1.59에 해당되는 최소 항로 폭이 필요한 것으로 분석되었다. 해당 결과는 우리나라 항로 설계기준의 개선 필요성 및 선박 대형화에 따른 통항 안전성 확보에 요구되는 최소 항로 폭 결정 등에 직접적으로 활용이 가능할 것이라 판단된다.

• 전자공학회논문지A
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• 제33A권10호
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.