• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.218-220
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• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.28-32
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• 2001

It was studied in the present work how the thermal cycling performance of LOC (lead on chip) packages depends on the package construct or leadframe materials. First, package body thickness and Au wire diameter were manipulated for the selection of proper package design. Secondly, two different types of leadframe materials (i.e. copper and 52%Fe-48%Ni alloy) were tested to determine the better material for improved reliability margin of plastically encapsulated microelectronic packages. This work shows that manipulating package body thickness was more effective than an increase of Au wire from 23$\mu\textrm{m}$ to 33$\mu\textrm{m}$ for the prevention of wire debonding failure. Further, this work indicates that the LOC packages including the copper leadframes can be more susceptible to thermal cycling reliability degradation due to chip cracking than those including the alloy leadframes.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.

• 대한임베디드공학회논문지
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• 제4권2호
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• pp.55-62
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• 2009

The power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to a rapid increase in the chip temperature as well. If the temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for Dynamic Thermal Management (DTM) have been proposed. In this paper, we propose a learning based temperature prediction scheme for a multi-core system. In this approach, from repeatedly executing an application, we learn the thermal patterns of the chip, and we control the temperature in advance through DTM. When the predicted temperature may go beyond a threshold value, we reduce the temperature by decreasing the operation frequencies of the corresponding core. We implement our temperature prediction on an Intel's Quad-Core system which has integrated digital thermal sensors. A Dynamic Frequency System (DFS) technique is implemented to have four frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average $5^{\circ}C{\sim}7^{\circ}C$. The overall average temperature reduced from $72^{\circ}C$ to $65^{\circ}C$.

• 한국융합학회논문지
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• 제10권11호
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• pp.95-100
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• 2019

본 논문은 자율 주행차량의 운행과 더불어 기존 차량 사고 방지를 위한 차량 간 통신 기술, 자율주행 기술, 브레이크 자동 제어 기술, 인공지능 기술 등이 널리 개발되고 있다. 차량 사고 발생이 일어나더라도 사망이나 부상을 최소화하기 위한 각종 기술들의 안전성의 상용화에 있다. 본 논문의 경우 자율주행 차량시, 안전성 확보연구이다. 이는 일반적인 저전력 근거리 무선 통신용 칩 신호나 초소형 도로 AI 장착 등의 공간적 요소에 따라 판별한다. 반면 본 논문은 상기 전자 칩의 신호를 읽는 데에서 생체 전자 칩까지의 "감지영역 내 체류 시간인식, 민감도"까지 체크하여 승차한 안전의 신뢰성을 높인다. 실제 세계 각국의 신뢰성을 실증한 결과로서, 안전성면에서 탑승객 전원의 안전 자율 시스템을 유도한다. 무인 자율차량 탑승과 상용화는 가까운 미래에 도로위 IoT의 AI 시스템과 생체 칩(Verification emotion + Chip)으로의 연계성면에서 그 진보성의 실증결과, 세계 각국의 안전 기술신뢰성은 더욱 부각된다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• 비파괴검사학회지
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• 제12권4호
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• pp.18-25
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• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.