• Title/Summary/Keyword: Lead-on-chip

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Evaluation of Thermal Deformation in Electronic Packages

  • Beom, Hyeon-Gyu;Jeong, Kyoung-Moon
    • Journal of Mechanical Science and Technology
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    • v.14 no.2
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    • pp.251-258
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    • 2000
  • Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

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Analysis of Power Noises by Chip-to-Chip Power Coupling on High-Speed Memory Modules (고속 메모리 모듈에서 칩 간의 파워커플링에 의한 파워 잠음 분석)

  • 위재경
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.31-39
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    • 2004
  • This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM and FBGA-based DIMH In controversy with common concepts, we find that the noise-isolation characteristics of FBGA package are more weak and sensitive on transferred noises than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.

Dosimetric characteristics of an independent collimator system using measurements performed quarter fields. (Tungsten eyeball shield block의 임상적용에 관한 고찰)

  • Jeong, Deok-Yang;Lee, Byoung-Koo;Hwang, Woong-Koo
    • The Journal of Korean Society for Radiation Therapy
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    • v.14 no.1
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    • pp.89-94
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    • 2002
  • During radiation therapy with electron beam to eyelid, we must keep the minimal dose on eyeball as possible. especially in the treatment of Sebaceous gland carcinoma, Squamouse cell ca., and basal cell ca. of eyelid and low grade MALToma etc. But if radiation field covered the upper & lower eyelid, it makes a cataract on lens of treated eye, in late complications. Now we reports the advantages of Tungsten eyeball shielding block compare to previously used lead block. with BOLX-I material, we made a eyeball model and measured the absorbed dose of 6MeV & 9MeV electron hem at 6 point of eyeball model with TLD chip. And compare the absorbed dose to previously lead block and other types of Tungsten eyeball shielding block.

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A Study on the Life Prediction and Quality Improvement of Joint in IC Package (플라스틱 IC 패키지 접합부의 수명예측 및 품질향상에 관한 연구)

  • 신영의;김종민
    • Journal of Welding and Joining
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    • v.17 no.1
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    • pp.124-132
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    • 1999
  • Thermal fatigue strength of the solder joints is the most critical issue for TSOP(Thin Small Outline Package) because the leads of this package are extremely short and thermal deformation cannot be absorbed by the deflection of the lead. And the TSOP body can be subject to early fatigue failures in thermal cycle environments. This paper was discussed distribution of thermal stresses at near the joint between silicon chip and die pad and investigated their reliability of solder joints of TSOP with 42 alloy clad lead frame on printed circuit board through FEM and 3 different thermal cycling tests. It has been found that the stress concentration around the encapsulated edge structure for internal crack between the silicon chip and Cu alloy die pad. And using 42 alloy clad, The reliability of TSOP body was improved. In case of using 42 alloy clad die pad(t=0.03mm). $$\sigma$_{VMmax}$ is 69Mpa. It is showed that 15% improvement of the strength in the TSOP body in comparison with using Cu alloy die pad $($\sigma$_{VMmax}$=81MPa). In solder joint of TSOP, the maximum equivalent plastic strain and Von Mises stress concentrate on the heel of solder fillet and crack was initiated in it's region and propagated through the interface between lead and solder. Finally, the modified Manson-Coffin equation and relationship of the ratio of $N_{f}$ to nest(η) and cumulative fracture probability(f) with respect to the deviations of the 50% fracture probability life $(N_{f 50%})$ were achieved.

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Process Capability Optimization of a LED Die Bonding Using Response Surface Analysis (반응표면분석법을 이용한 LED Die Bonding 공정능력 최적화)

  • Ha, Seok-Jae;Cho, Yong-Kyu;Cho, Myeong-Woo;Lee, Kwang-Cheol;Choi, Won-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4378-4384
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    • 2012
  • In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. This paper focuses on the process optimization of a LED die bonding, which attaches small zener diode chip on PLCC LED package frame, using response surface analysis. Design of experiment (DOE) of 5 factors, 3 levels and 5 responses are considered, and the results are investigated. As the results, optimal conditions those satisfy all response objects can be derived.

The Chip Bonding Technology on Flexible Substrate by Using Micro Lead-free Solder Bump (플렉서블 기반 미세 무연솔더 범프를 이용한 칩 접합 공정 기술)

  • Kim, Min-Su;Ko, Yong-Ho;Bang, Jung-Hwan;Lee, Chang-Woo
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.3
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    • pp.15-20
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    • 2012
  • In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

A Study on the Effects of Package and PCB Materials on Thermal Characteristics of PDIP (패키지 및 PCB 재료가 PDIP 열특성에 미치는 영향에 관한 연구)

  • 정일용;이규봉
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.18 no.3
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    • pp.729-737
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    • 1994
  • A three-dimensional finite element model of a 20-pin plastic dual-in-line package(PDIP) plugged into a PCE has been developed by using the finite element code ANSYS. The model has been used for thermal characterization of the package during its normal operation under natural convection cooling. Temperature distributions in the package and PCB are obtained from numerical analysis and compared with experimentally measured data. Various cases are assumed and analyzed to study the effects of package and PCB materials on thermal characteristics of PDIP with and without aluminum heatspreader. Thermal dissipation capability of PDIP is greatly increased due to copper die pad/lead frame and heatspreader. However, thermally induced stresses in the package and fatigue life of chip are improved for PDIP with Alloy 42 die pad/lead frame and no heatspreader. It is also found that the role of PCB on thermal characteristics of PDIP is very imporatant.

Design by Topology Optimization and Performance Test of Ultrasonic Bonding Module for Flip-Chip Packaging (초음파 플립칩 접합 모듈의 위상최적화 설계 및 성능 실험)

  • Kim, Ji Soo;Kim, Jong Min;Lee, Soo Il
    • Journal of Welding and Joining
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    • v.30 no.6
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    • pp.113-119
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    • 2012
  • Ultrasonic bonding is the novel packaging method for flip-chip with high yield and low-temperature bonding. The bonding module is a core part of the bonding machine, which can transfer the ultrasonic energy into the bonding spot. In this paper, we propose topology optimization technique which can make new design of boding modules due to the constraints on resonance frequency and mode shapes. The designed bonding module using topology optimization was fabricated in order to evaluate the bonding performance and reliable operation during the continuous bonding process. The actual production models based on the proposed design satisfied the target frequency range and ultrasonic power. The bonding test was performed using flip-chip with lead-free Sn-based bumps, the results confirmed that the bonding strength was sufficient with the designed bonding modules. Also the performance degradation of the bonding module was not observed after the 300-hour continuous process with bonding conditions.

DI water Nozzle Design for Effective Removal of the Particles Generated during Wafer-sawing (Wafer-Sawing시 발생하는 particle을 효과적으로 제거하기 위한 DI water 노즐의 최적 설계)

  • 김병수;이기준;이성재
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.4
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    • pp.53-60
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    • 2003
  • CCD(Charge-Coupled Device) wafers, with a layer of micro lenses on top, usually are not passivated with dielectric films. Micro lenses, in general, are made of polymer material, which usually has a large affinity for particles generated in the various chip fabrication processes, most notably the wafer sawing for chip-dicing. The particles deposited on the micro lens layer either seriously attenuate or deflect the incoming light and often lead to CCD failure. In this study we introduce new type of saws which would significantly reduce the particle-related problems found in conventional type of saws. In the new saws, the positions and diverging angles of side and center nozzles have been optimized so as to flush the particles effectively. In addition, an independent nozzle is added for the sole purpose of flushing the generated particles. The test results show that, with the new saws. the ratio of the particle-related CCD chip failures has been dropped drastically from 9.1% to 0.63%.

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The Low Height Looping Technology for Multi-chip Package in Wire Bonder (와이어 본더에서의 초저 루프 기술)

  • Kwak, Byung-Kil;Park, Young-Min;Kook, Sung-June
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.1 s.18
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    • pp.17-22
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    • 2007
  • Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

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