Browse > Article

Analysis of Power Noises by Chip-to-Chip Power Coupling on High-Speed Memory Modules  

위재경 (숭실대학교 공과대학 정보통신공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.10, 2004 , pp. 31-39 More about this Journal
Abstract
This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM and FBGA-based DIMH In controversy with common concepts, we find that the noise-isolation characteristics of FBGA package are more weak and sensitive on transferred noises than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.
Keywords
TSOP; FBGA; Impedance profiles; Power Coupling; DIMM;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Y. Eo, W. R. Eisenstadt 'A Compact Multilayer IC Package Model for Efficient Simulation, Analysis, and Design of High-performance VLSI Circuits,' IEEE Transactions on Advanced Packaging, vol. 26, no. 4, pp. 392-401, Aug. 2003   DOI   ScienceOn
2 S. M. Lee Y.-J. Kim, G. Moo, S. Lee, and J.-K. Wee, 'A Lumped-Circuit-Model-Based Design Method for Power Distribution Networks of Digital Circuit System', 7th IEEE Workshop on Signal Propagation on Interconnects' 2003, (Siena, Italy), pp.171-174. May 2003
3 D. Herrel and B. Becker, 'Modeling of power distribution system for high performance microprocessors,' IEEE Transaction on Advanced Packaging, vol.22, no.3, pp.240-248, Aug. 1999   DOI
4 W. H. Ryo, H. Fahmy, and H. Maramis, 'High Frequency Simultaneous Switching Output Noise (SSO) Simulation Methodology For a DDR333/400 Data Interface,' Ansoft High-Speed Design Forum, July 2002
5 J.-H. Choi, Y.-J. Kim, J.-K. Wee, and S. Lee, 'Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems' IEICE trans. on Electronics, Vol. E87-C, No.4, pp629-633, April, 2004
6 M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. Gielen, and H. De Man, 'Modeling and Experimental Verification of Substrate Noise Generation in a 220-Kgates WLAN System-on-Chip with Multiple Supplies', IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp, 1250-1260, Jul. 2003   DOI   ScienceOn
7 A. Waizman and C.-Y. Chung, 'Resonant Free Power Network Design Using Extended Adaptive Voltage Positioning(EAVP) Methodology,' IEEE Transactions on Advanced Packaging, vol. 24, no. 3, pp. 236-245, Aug. 2001   DOI   ScienceOn