• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.4A
• /
• pp.466-471
• /
• 2004

This paper proposes an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. 1-Pixel Fingerprint sensor circuit was designed and simulated, and the layout was performed.

• International Journal of Industrial Entomology and Biomaterials
• /
• v.6 no.1
• /
• pp.1-9
• /
• 2003

The silkworm, Bombyx mori, is prone to infection of various pathogenic organisms. Pebrine, one of the deadliest disease of silkworm caused by highly virulent parasitic microsporidian, Nosema bombycis has been understood since long. Infections of the disease range from chronic to highly virulent and can result in complete loss to the sericulture industry. Several strains and species of microsporidians have since been isolated from the infected silkworms; the disease is becoming increasingly more and more complex. Epizootiology, development of immunodiagnostic kit, use of chemotherapy and thermotherapy techniques has been addressed for identification and control of the disease. A technique of delayed mother moth examination, which plays a decisive role in the detection of the disease and harvestation of stable cocoon crop, has been described. An attempt has been made to review briefly the literature available on various aspects of the pebrine disease in order to develop efficient model(s) for the prevention and control of the disease and to suggest future avenues of investigation in the field of pebrine disease management.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1525-1527
• /
• 1987

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.

• Journal of information and communication convergence engineering
• /
• v.6 no.1
• /
• pp.43-46
• /
• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.448-449
• /
• 2018

최근, WBG 반도체 소자에 대한 연구가 활발히 진행됨에 따라 고속 스위칭으로부터 발생되는 문제점들을 해결하기 위한 여러 방안들이 제시되고 있다. WBG 반도체 소자의 안정적인 고속 스위칭을 실현하기 위해서는 게이트 드라이버 내에 존재하는 기생 인덕턴스를 최소화하는 것이 가장 중요하다. 본 논문에서는 layout의 최적화 설계를 통해 GaN FET 구동용 게이트 드라이버 내의 기생 인덕턴스를 최소화할 수 있는 방안을 제시하고 설계를 통해 만들어진 게이트 드라이버를 실험을 통해 스위칭 특성을 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.44-53
• /
• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.7
• /
• pp.7-16
• /
• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.3
• /
• pp.101-108
• /
• 2004

A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.46-52
• /
• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1297-1303
• /
• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.