• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of Communications and Networks
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• v.12 no.2
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• pp.168-173
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• 2010

Error concealment techniques are significant due to the growing interest in imagery transmission over error-prone channels. This paper presents a spatial error concealment technique for losslessly compressed images using least significant bit (LSB)-based data hiding to reconstruct a close approximation after the loss of image blocks during image transmission. Before transmission, block description information (BDI) is generated by applying quantization following discrete wavelet transform. This is then embedded into the LSB plane of the original image itself at the encoder. At the decoder, this BDI is used to conceal blocks that may have been dropped during the transmission. Although the original image is modified slightly by the message embedding process, no perceptible artifacts are introduced and the visual quality is sufficient for analysis and diagnosis. In comparisons with previous methods at various loss rates, the proposed technique is shown to be promising due to its good performance in the case of a loss of isolated and continuous blocks.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.11
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• pp.4537-4556
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• 2020

This research was based on the study conducted by Khodaei et al. (2012), namely, the least-significant-bit (LSB) substitution combined with the pixel-value differencing (PVD) steganography, and presented an improved irreversible image steganography method. Such a method was developed through integrating the improved LSB substitution with the modulus function-based PVD steganography to increase steganographic capacity of the original technique while maintaining the quality of images. It partitions the cover image into non-overlapped blocks, each of which consists of 3 consecutive pixels. The 2nd pixel represents the base, in which secret data are embedded by using the 3-bit LSB substitution. Each of the other 2 pixels is paired with the base respectively for embedding secret data by using an improved modulus PVD method. The experiment results showed that the method can greatly increase steganographic capacity in comparison with other PVD-based techniques (by a maximum amount of 135%), on the premise that the quality of images is maintained. Last but not least, 2 security analyses, the pixel difference histogram (PDH) and the content-selective residual (CSR) steganalysis were performed. The results indicated that the method is capable of preventing the detection of the 2 common techniques.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.575-578
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• 2003

SPIHT algorithm is a wavelet based fast and effective technique for image compression. It uses a list structure to store status information which is generated during set-partitioning of zero-tree. Usually, this requires lots of additional memory depending on how high the bit-rate is. Therefore, in this paper, we propose a new technique called MZP-DFS, which needs no additional memory when running SPIHT algorithm. It traverses a spatial-tree according to DFS and eliminates additional memory as it uses test-functions for encoding and LSB bits of coefficients for decoding respectively. This method yields nearly the same performance as SPIHT. This may be desirable in hardware implementation because no additional memory is required. Moreover. it exploits parallelism to process each spatial-tree that it can be applied well in real-time image compression.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.321-327
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• 2004

SPIHT algorithm is a wavelet based fast and effective technique for image compression. It uses a list structure to store status information which is generated during set-partitioning of toro-tree. Usually, this requires lots of additional memory depending on how high the bit-rate is. Therefore, in this paper, we propose a new technique called MZC-BFS, which needs no additional memory when running SPIHT algorithm. It explicitly performs a breadth first search of the spatial-tree using peano-code and eliminates additional memory as it uses pre-status significant test for encoding and LSB bits of some coefficients for decoding respectively. This method yields nearly the same performance as SPIHT. This may be desirable in fast and simple hardware implementation and reduces the cost of production because no lists and additional memory are required.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.137-142
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• 2001

Since recent production system becomes that of the small quantity, large volume with high quality production, accurate and high speed inspection system is required. In such situation, noncontact 3D measurement system which utilized CCD cameras is useful technique in terms of system cost, speed of data acquisition, measuring accuracy and application. However, it has low accuracy compared with contact 3D measurement system because of the camera distortion, non uniformity of laser distribution and so on. For those reasons, in this paper precision enhancement method is studied considering radial camera distortion, and laser distribution. A distortion correction method is applied even to the standard lens. The laser slit beam trajectory is determined by 3 method: based of the Gaussian function signal approximation, the median method, the center of gravity method and the peak point of the Gaussian function method.