Browse > Article

A 10b 100MS/s 0.13um CMOS D/A Converter Based on A Segmented Local Matching Technique  

Hwang, Tae-Ho (Dept. of Electronic Engineering, Sogang University)
Kim, Cha-Dong (Dept. of Electronic Engineering, Sogang University, Dongbu HiTek Co., Ltd)
Choi, Hee-Cheol (Aptina Korea)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.4, 2010 , pp. 62-68 More about this Journal
Abstract
This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.
Keywords
CMOS; DAC; current-steering; segmented local matching; double-cascode;
Citations & Related Records
연도 인용수 순위
  • Reference
1 A. van den Bosch. M. Borremans, M. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001.   DOI   ScienceOn
2 M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.   DOI   ScienceOn
3 J. Deveugele and M. Steyaert, "A 10-bit 250-MS/s binary-weighted current-steering DAC," IEEE J. Solid-State Circuits, vol. 41, pp. 320-329, Feb. 2006.   DOI   ScienceOn
4 T. Chen and G. G. E. Gielen, "A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration," IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2386-2394, Nov. 2007.   DOI
5 A. Van den Bosch, M. Steyaert, and W. Sansen, "The extraction of transistor mismatch parameters : The CMOS current-steering D/A converter as a test structure," in Proc. IEEE Int. Symp. on Circuits and Systems(ISCAS), pp. 745-748, May 2000.
6 J. Bastos, A. M. Marques, M. Steyaert, and W. Sansen, "A 12-Bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.   DOI   ScienceOn
7 G. Van der Plas, J. Van den bussche, W. Sansen, M. Steyaert, and G. G. E. Gielen, "A 14-bit intrinsic accuracy $Q^{2}$ random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.   DOI   ScienceOn
8 A. R. Bugeja and B. S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.   DOI   ScienceOn
9 B. Nejati and L. Larson, "An area optimized 2.5V 10-b 200-MS/s 200-uA CMOS DAC," in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 161-164, Sept. 2006.
10 B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
11 C. Lin and K. Bult, "A 10-b 500-MSample/s CMOS DAC in $0.6mm^{2}$," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.   DOI   ScienceOn
12 Y. Cong and R. L. Geiger, "A 1.5-V 14-bit 100-MS/s self-calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, pp. 2051-2060, Dec. 2003.   DOI   ScienceOn
13 O. Matsumoto, H. Harada, Y. Morimoto, T. Kumamoto, T. Miki, and M. Hotta, "An 11-bit 160-MS/s 1.35-V 10-mW D/A convertar using automated device sizing system," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 809-814, Jan. 2005.
14 K. L. Chan, J. Zhu, and I. Galton, "A 150MS/s 14-bit segmented DEM DAC with greater than 83dB of SFDR across the Nyquist band," in Symp. VLSI Circuits Dig. Tech. Papers, pp. 200-201, June, 2007.
15 A. Van den Bosch, M. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters," in Proc. IEEE Int. Conf. Electronics, Circuits and Systems(ICECS), pp. 1193-1196, Sept. 1999.