• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.1
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• pp.25-33
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• 1998

In this paper, we describe a single-gate MESFET mixer at PCS(Personal Communication Service) frequency band. The PCS frequency band is 1965~2025 MHz in FR and 140 MHz in IF irrespectly. The design of the mixer was executed by microwave simulator, EEsof Libra. The matching network is consisted of rectangular inductor, MIM capacitor and open stub. The ma- nufacture work was accomplished by the micro-pen and wedge-bonder. The mixer showed $6.69\pm0.65$ dB of conversion gain, $-14.9\pm3.5$dB of RF reflection coefficient and 57.83 dB of LO/IF isolation at 10 dBm of LO power when LO frequency is 1855 MHz. When this mixer is used at PCS terminal, IF-amplifier which compensates the conversion loss of diode mixer may be omitted.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1114-1122
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• 2005

In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.2
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• pp.178-185
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• 1996

In this paper, a theoretical analysis of a wide band distributed mixer using a dual-gate GaAs MESFET's(DGFET) is introduced. Based on low noise mixer mode(LNM) region modeling of DGFET, variation of g/sub m/ and conversion gain are presented versus bias. The distributed mixer is composed of drain and gate transmission line, m-derived image impedance matching circuits at each input and output port, and DGFET's. Through computer simulation, wide-band characteristics of designed distributed mixer are confirmed. And, it is certificated that LO/RF isolation between gate 1 and gate 2 is obtained more than 15dB.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.339-342
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• 2004

본 논문은 밀리미터파 대역 무선통신 시스템 송신부의 응용을 위해 CPW 구조를 이용하여 V-band용 상향 주파수 혼합기와 2단 구동증폭기를 설계$\cdot$제작하였다. 능동소자는 본 연구실에서 제작한 $0.1{\mu}m$ 게이트 GaAs Pseudomorphic HEMTs(PHEMTs)를 사용하였으며 입$\cdot$출력단은 CPW를 사용해 정합 회로를 설계하였다. 제작된 상향 주파수 혼합기는 LO power 5.4 dBm, 2.4 GHz IF 신호를 -10.25 dBm으로 입력하였을 때 Conversion Loss 1.25 dB, LO-to-RF Isolation은 58 GHz에서 13.2 dB의 특성을 나타내었다 2단 구동 증폭기는 측정결과 60 GHz에서 S21 이득 13 dB, $58\;GHz\;\~\;64\;GHz$ 대역에서 S21 이득 12 dB 이상을 유지하는 광대역 특성을 얻었고 증폭기의 Pl dB는 3.8 dBm, 최대 출력전력은 6.5 dBm의 특성을 얻었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.143-149
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• 2004

This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.341-346
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• 2014

This paper has presented the design and fabrication of phase correlator for wideband digital frequency discriminator (DFD) operating over the 6.0 to 18.0 GHz frequency range. Fabricated DFD phase correlator has been measured I or Q output signal, and analyzed frequency discrimination error. The operation of the proposed mixer type correlator has been analyzed by deriving some analytic equations. To design the phase correlator, this paper has modeled and simulated IQ mixer and 8-way power divider by using RF simulation tool. Designed phase correlator has fabricated and measured. The phase error and frequency discrimination error have been presented using by measured I and Q output signal. Over the 6.0~18.0 GHz range, the root mean square(RMS) phase error is $4.81^{\circ}$, RMS and frequency discrimination error is 1.49 MHz, RMS.