• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.773-776
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• 2001

열악한 전송 환경에서 고품질, 고신뢰성 통신을 지속적으로 하기 위해서 오류 정정 부호는 필수 적이다. 최근에 반복 복호를 통해 샤논의 채널 용량 한계에 근접하는 터보 부호와 LDPC부호가 가장 관심을 불러일으키고 있다. 반복 복호법은 성능 면에서는 우수해 지나 이에 따른 계산량 증가와 지연이 수반된다. 따라서 본 논문에서는 모의 실험을 통한 수신 데이터를 이용, SNR을 추정하여 LDPC 부호의 최대 반복 복호수에 따른 계산량과 지연을 효과적으로 줄일 수 있는 적응적 반복 복호수 설정 방식을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.924-933
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• 2008

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.229-232
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• 2012

This paper describes performance evaluation using fixed-point Matlab modeling and simulation, and hardware design of LDPC decoder which is based on Improved Normalized Min-Sum(INMS) decoding algorithm. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard. Considering hardware complexity, it is designed using a block-serial(partially parallel) architecture which is based on layered decoding scheme. A DFU based on sign-magnitude arithmetic is adopted to minimize hardware area. Hardware design is optimized by using INMS decoding algorithm whose performance is better than min-sum algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.229-231
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• 2011

H.264/AVC와 같은 동영상 압축 기술은 동영상의 압축에 필요한 연산이 대부분 부호기에서 이루어진다. 반면에 분산 동영상 압축 기법은 정보 압축에 필요한 연산이 대부분 복호기에서 수행되는 구조를 가진다. 본 논문에서는 분산 동영상 압축 기법의 구성 요소 중 오류 정정 부호기와 복호기에 사용되는 오류 정정 부호 중 LDPC 부호의 성능을 향상 시킬 수 있는 새로운 복호 기법을 제안한다. 제안하는 기법을 적용하여 추가적인 연산 없이 LDPC 부호의 오류 정정 성능을 향상시킬 수 있었다.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2023-2024
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• 2006

1962년 Gallager에 의해 처음 제안된 LDPC 부호는 복호를 수행하는 부호방식으로 패리티 행렬(H)의 대부분이 0으로 구성되어 복호시에 적은 연산량을 요구하며, shannon의 한계에 도달하는 복호 능력으로, 차세대 통신의 주된 부호 방식으로 고려되고 있다. 하지만, LDPC는 부호화에 있어서 여타 다른 부호방식에 비해 복잡한 특성을 가지고 있으므로, 이를 개선하기 위한 부호방식의 적용이 필요하다. 본 논문에서는 효율 적인 부호화를 위하여 Dual-diagonal H parity행렬을 구성 하고, 쉽게 부호 길이를 확장 할 수 있는 Quasi-Cyclic 방식을 적용한 복호기를 구현하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.325-333
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• 2010

Most communication systems including Wibro use quasi-cyclic LDPC codes composed of circulants. However, it is very difficult to design quasi-cyclic(QC) LDPC codes with optimal degree distribution satisfying conditions on layered decoding and girth due to the restriction of the size of its base matrix. In this paper, we propose a good solution by introducing superposition matrices to QC LDPC codes. We derive the conditions on checking girth of QC LDPC codes with superposition matrices, and propose new decoder to support layered decoding both for original QC LDPC codes and their modifications with superposition matrices. Simulation results show considerable improvements to convergence speed and error-correcting performance of proposed scheme which adopts QC LDPC codes with superposition matrices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1143-1149
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• 2006

In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.