• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.487-488
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• 2015

New inverter motor drive systems consume 30%~50% less energy compared to existing motor drive systems. For inverter motor drive systems, the development of a 1200V high side driver is critical. This paper presents an advanced 1200V high side driver with low power consumption and high ruggedness. This solution implements a high voltage level shifter which consumes low power by adding a clamped VGS LDMOS driver to the conventional short pulse generator. Moreover, this paper proposes a highly rugged 1200V LDMOS which improves SOA by limiting the hole current. This paper could be applied to smart power modules used for HVAC (heating, ventilation, and airconditioning) and industrial inverters. Consequently, this paper will provide design engineers with an understanding of how they can make a significant contribution to worldwide energy savings.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.156-158
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• 2002

Reduction of on-resistance($R_{on}$) in high voltage devices is of critical importance for the power consumption of the device. $R_{on}$ decreases with increase of the doping concentration of the drift region. However, breakdown voltage(BV) decreaes also with increase of doping concentration. In this report, a multi-resurf LDMOS[1] strcuture is proposed to reduce the $R_{on}$ which allows no degradation in BV. The on-and off-state characteristics of the proposed structure are simulated using the two-dimensional devices simulator ATLAS and compared with those from the conventional structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.45-53
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• 2015

Power 소자 기술은 digital & mixed signal device와 on-chip 구현을 위해서 CMOS 공정에 대한 기본 이해가 필요하다. CMOS 공정 기반 위에 power device 공정을 추가하면서 다양한 operation voltage의 power 소자를 구현하고, passive device 들을 동일 공정에서 구현하여 다양한 components 들로 power IC 제품을 design 할 수 있도록 modular process를 제공하는 것이 중요하다. 또한 power device로 주로 사용되는 LDMOS 소자에 대한 performance 개선을 위해 simulation을 통해 key device parameter들의 특성을 예측하고, 구조를 설계하는 것이 Si process 전에 중요한 일 중의 하나이다. 아울러 power management가 potable power, consumer electronics 및 green energy에서 가장 빠르게 성장하는 분야이므로, 차별화된 power 소자 기술을 확보하여 급변하는 시장 환경에 대응하는 것이 필요하다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.2
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• pp.85-89
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• 2011

In this paper, a novel Class-E power amplifier using metamaterials has been realized with one RF LDMOS diffusion metal-oxide-semiconductor field effect transistor. The CRLH structure can lead to metamaterial transmission line with the Class-E power amplifier tuning capability. The CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Also, the proposed power amplifier has been realized by using the CRLH structure in the output matching network for better efficiency. Operating frequencies are chosen at 13.56 MHz in this work. The measured results show that the output power of 39.83 dBm and the gain of 11.83dB was obtained. At this point, we have obtained the power-added efficiency (PAE) of 73 % at operation frequency.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.556-561
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• 2016

This paper describes implementation of a 13.56 MHz, 5 kW RF high power generator for ISM band applications. This RF generator consists of four LDMOS modules of 1.25kW class-AB push-pull power amplifier with drive amplifier and its outputs are combined by using Wilkinson type transmission-line transformers. Its generator has a high efficiency and output power better than linearity. In order to discharge power transistor heats, we used on water cooled copper plate. Also, these have a composite circuit of combiner and low-pass filter and safety circuit to detector over and reflected power. The RF generator has achieved a efficiency of 79 % at 5.33 kW of saturated power level experimentally.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.40-47
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• 2009

This paper presents new drain bias scheme for the linearity enhancement of envelope tacking power amplifiers for W-CDMA base-stations. In the conventional envelope tracking power amplifiers, the drain bias voltage is lowered close to the knee voltage of transistor, resulting in the severe linearity degradation. To solve this problem, it is proposed in this paper that the amplifier is biased in the conventional class AB mode with a fixed drain bias voltage if the input envelope is low and in the envelope tracking mode otherwise. Moreover, the drain bias in the envelope tracking mode is newly determined to minimized the distortion. To verify the effectiveness of the proposed bias scheme, simulation is performed on the W-CDMA based-station envelope tracking power amplifier using class AB Si-LDMOS power amplifier. It is shown from the simulation that the proposed bias scheme allows a drastic linearity enhancement with the comparable efficiency enough to meet the requirement of W-CDMA base-station without additional linearization techniques.