• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1938-1940
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• 1999

Trench-Gate structures are proposed to improve the breakdown voltage of LDMOS as well as the second breakdown under forward biased gate. Two dimensional device simulator PISCES II has been used to explain the effects of the drift layer thickness on the breakdown voltage of the conventional LDMOS and Trench Gate LDMOS in terms of potential contour lines. The Trench Gate structure has shown improvements in the breakdown voltage by about 44% and 84% for $V_G$=0 V and $V_G$=15 V respectively.

• ETRI Journal
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• v.21 no.3
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• pp.22-28
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• 1999

A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURE (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at $V_{gs}$=-0.5V, the specific on-resistance of the LDMOS with the tapered field oxide is about $31.5{\Omega}{\cdot}cm^2$, while that of the LDMOS with the conventional field oxide is about $57m{\Omega}{\cdot}cm^2$.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1424-1426
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• 2001

본 논문에서는 채널과 드리프트 영역을 트랜치 안쪽에 형성하여 소자 크기를 줄임으로서 항복전압을 감소시키지 않고 낮은 온 저항을 얻을 수 있는 새로운 수직방향 채널 LDMOS(Lateral Double Diffused MOSFET)를 제안한다. 기존의 LDMOS 구조와 비교 할 때 동일한 60V의 항복 전압에서 소자 크기가 4${\mu}m$로 줄어들었고 이에 따라 온 저항은 절반의 수준으로 (0.45 m${\Omega}cm^2$) 감소하였다. 또한 소자 크기의 감소로 인해 전력용 집적회로를 구성할 때 집적도가 두 배 가량 증가하게 된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.377-380
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• 2003

An Analytic breakdown voltage model of LDMOS with internal field ring is proposed. The model is a simple analytic formula which has variables such as the dimension of drift retion, the position and doping concentration of the internal field ring, the thickness and permittivity of oxide. By comparing the results from two dimensional TCAD simulation, the proposed model explains the breakdown phenomena fairly well.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.361-364
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• 2004

Surface doped SOI RESURF LDMOSFET with recessed source region is proposed to improve the on- and off-state characteristics. Surface region of the proposed LDMOS structure is doped like step. The characteristics of the proposed LDMOS is verified by two-dimensional process simulator ATHENA and device simulator ATLAS[1]. The numerically calculated on-resistance($R_{ON}$) of the proposed LDMOS is $10.36\Omega-cm$ and breakdown voltage is 205V when $L_{dr}=7{\mu}m$ with step doped surface.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.81-86
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• 2005

In this paper, we present an efficiency extension of Doherty power amplifier using LDMOS FET devices with different peak output powers and an unequal power divider. The amplifier is designed by using a MRF21045 with P1 dB of 45 W as the main amplifier biased for Class-AB operation and a MRF21090 with P1 dB of 90 W as the peaking amplifier biased for Class-C operation. The input power is divided into a 1:1.5 power ratio between the main and peaking amplifier. The simulated results of the proposed Doherty amplifier shows an efficiency improvement of approximately 19 % in comparison to the class-AB amplifier at an output power of 42.5 dBm. The fabricated Doherty amplifier obtained a PAE of 33.68 % at 9 dB backed off from P1 dB of 51.5 dBm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.13-20
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• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.187-190
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• 2005

In this dissertation, a temperature characteristics of the LDMOS is proposed by the method of changing the gate voltage to find the optimum points when the IMD characteristics is changed by the atmosphere temperature. Experimental results have good agreement with the ADS simulation about the 3rd and 5th IMD when the gate voltage is changed with the fixed temperature.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1451-1453
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• 2001

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with graded gate and recessed source is proposed. The proposed structure can increase the breakdown voltage by reducing the electric field crowding at the edge of gate. Simulation results by TSUPREM4 and MEDICI have shown that the breakdown voltage of proposed device was found to be 52 V while that of conventional device was 45 V. At the same breakdown voltage of 45 V, the on-resistance of the LDMOS with graded gate and recessed source was 14.4 % lower than that of conventional structure.