• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.403-408
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• 2008

In this paper, the high efficiency and linearity Doherty power amplifier using DGS and adaptive bias technique has been designed and realized for 2.3GHz WiBro applications. The Doherty amplifier has been implemented us-ing silicon MRF 281 LDMOS FET. The RF performances of the Doherty power amplifier (a combination of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class AB amplifier alone, and conventional Doherty amplifier. The Maximum PAE of designed Doherty power amplifier with DGS and adaptive bias technique has been 36.6% at 34.01dBm output power. The proposed Doherty power amplifier showed an improvement 1dB at output power and 7.6% PAE than a class AB amplifier alone.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1254-1264
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• 2008

This paper suggests an extended memory polynomial model that improves accuracy in modeling memory effects of RF power amplifiers(PAs), and verifies effectiveness of the suggested method. The extended memory polynomial model includes cross-terms that are products of input terms that have different delay values to improve the limited accuracy of basic memory polynomial model that includes the diagonal terms of Volterra kernels. The complexity of the memoryless model, memory polynomial model, and the suggested model are compared. The extended memory polynomial model is represented with a matrix equation, and the Volterra kernels are extracted using least square method. In addition, the structure of digital predistorter and digital signal processing(DSP) algorithm based on the suggested model and indirect learning method are proposed to implement a digital predistortion linearization. To verify the suggested model, the predicted output of the model is compared with the measured output for a 10W GaN HEMT RF PA and 30 W LDMOS RF PA using 2.3 GHz WiBro input signal, and adjacent-channel power ratio(ACPR) performance with the proposed digital predistortion is measured. The proposed model increases model accuracy for the PAs, and improves the linearization performance by reducing ACPR.

• Journal of Power Electronics
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• v.18 no.2
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• pp.640-650
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• 2018

A TRIAC dimmable LED driver with a wide tuning range and a two-stage uniform dimming scheme is proposed in this paper. To solve the restricted dimming range problem caused by the limited conduction ratio of TRIAC dimmers, a conduction ratio compensation technique is introduced, which can increase the output current up to the rated output current when the TRIAC dimmer turns to the maximum conduction ratio. For further optimization, a two-stage uniform dimming diagram with a rapid dimming curve and a slow dimming curve is designed to make the LED driver regulated visually uniform in the whole adjustable range of the TRIAC dimmer. The proposed control chip is fabricated in a TSMC $0.35{\mu}m$ 5V/650V CMOS/LDMOS process, and verified on a 21V/500mA circuit prototype. The test results show that, in the 90V/60Hz~132V/60Hz ac input range, the voltage linear regulation is 2.6%, the power factor is 99.5% and the efficiency is 83%. Moreover, in the dimming mode, the dimming rate is less than 1% when the maximum dimming current is 516mA and the minimum dimming current is only about 5mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.719-726
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• 2008

In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1406-1407
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• 2006

본 논문에서는 기존의 250V급 트렌치 전극형 파워 MOSFET을 구조적으로 개선하여, 600V 이상의 순방향 항복 전압을 갖는 파워 MOSFET을 설계 하였다. 본 논문에서 제안한 구조로 기존의 250V급 트렌치 전극형 파워 MOSFET에 비하여 더욱 높은 순방향 항복 전압을 얻었다. 또한, 기존의 LDMOS 구조로 500V 이상의 항복 전압을 얻기 위해서 $100{\mu}m$ 이상의 크기를 필요로 했던 반면에, 본 논문에서 제안한 소자의 크기(vertical 크기)는 $50{\mu}m$로서, 소자의 소형화 및 고효율화 측면에서 더욱 우수한 특성을 얻었다. 본 논문은 2-D 공정시뮬레이터 및 소자 시뮬레이터를 바탕으로, 트렌치 옥사이드의 두께 및 폭, 에피층의 두께 변화 등의 설계변수와 이온주입 도즈 및 열처리 시간에 따른 공정변수에 대한 시뮬레이션을 수행하여, 본 논문에서 제안한 구조가 타당함을 입증하였다.

• Journal of Semiconductor Engineering
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• v.3 no.2
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.276-282
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• 2015

Until recently, power amplifiers using LDMOS were Class-AB and Doherty type, and showed 55 % efficiency for narrowband of 60 MHz bandwidth. However, owing to the RRH application of base stations power amplifier module, a bandwidth expansion of at least 100 MHz and high efficiency power amplifiers of at least 60 % power efficiency are required. In this study, a Class-J power amplifier was designed by optimizing an output matching circuit so that the second harmonic load will contain a pure reactance element only and have broadband characteristics by using GaN HEMT. The measurements showed that a 45 W Class-J power amplifier with a power added efficiency of 60~75 % was achieved when continuous wave signals were input at 1.6~2.3 GHz, including W-CDMA application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.262-267
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• 2005

During several method of improvement efficient, We analyzed Doherty Amplifier That used by simple circuit and 180w PEP LDMOS to analyze improvement of efficient and linearity. We for testing performance of Doherty Amplifier compared with Balanced Class AB, the experimental results show when Peaking Amp $V_gs.P$=1.53V, the efficiency is increased at Maximum 11.6$\%$. After finding optimum bias point of linearity improvement by manual tuning gate bias, when WCDMA 4FA $V_gs.P$=3.68V IMSR could be increased maximum 3.34dB. especially, when we match bias point of Peaking amp at 1.53V, we could get a excellent efficiency increase and have fUR under -3203c at output power 43dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1010-1019
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• 2005

In this paper, we used neural network technique to model memory effects of RF power amplifier which is fed by two-tone input signals. The memory effects in power amplifier were identified by observing the unsymmetrical distribution of IMD(Inter-Modulation Distortion) measurements with the change of tone spacings and power levels. Different asymmetries of IMD were also found at different center frequencies. We applied TDNN technique to model LDMOS power amplifier based on two tone IMD data, and the accuracy was very high compared to other modeling methods such as the(memoryless) adaptive modeling method.