• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.1
• /
• pp.1-6
• /
• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1105-1108
• /
• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.3
• /
• pp.478-485
• /
• 1987

Optimization of the sub-micron N-channel MOSFET with the LDD(Lightly Doped Drain)structure has been investigated. LDD devices with various length of n-region, n-dose and n-implantation species were fabricated for this purpose. It will be shown that LDD devices have lower substrate current by an order of magnitude and higher breakdown voltage than the conventional devices with comparable channel length. Optimized LDD structure has been found when the sidewall thickness is 2500\ulcorner and n-region is phosphorus implantd with the dose of 1.0E13/cm\ulcorner It has been found that transconductance degradation is less than 20%.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.2
• /
• pp.324-331
• /
• 1995

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.7
• /
• pp.522-526
• /
• 1998

We have fabricated a LDD structured polysilicon thin film transistor with low leakge current and the optimized LDD length has been obtained. The device performance is improved is improved by hydrogen passivation process. The on.off current ratio of poly0Si TFT s with $0.5{\mu}m$ and $1.0{\mu}m$ LDD length is much higher than that of conventional structured device due to the decrease of leakege current. The optimized LDD length may be $0.5{\mu}$ from the experimental data such as on/off current ratio, threshold voltage and hydrogenation effect.

• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.735-736
• /
• 1998

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure. (1) conventional ${\underline{S}}urface$ type ${\underline{L}}DD$(SL), (2) ${\underline{B}}uried$ type ${\underline{L}}DD$(BL), (3) ${\underline{S}}urface$urface ${\underline{I}}mplantation$ type LDD(SI). As a result, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.3
• /
• pp.391-395
• /
• 1998

The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8$\mu\textrm{m}$ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.

• Proceedings of the KIPE Conference
• /
• 2002.07a
• /
• pp.163-165
• /
• 2002

LDD구조를 가진 LDMOS 전력소자의 LDD영역과 채널영역변화에 의한 전기적 특성을 비교 조사하였다. MEDICI 시뮬레이션 tool을 이용하여 hot-carrier전류의 특성, ON 저항의 변화, breakdown 전압의 특성과 switch transient 특성을 조사하였다. Gate-drain 사이의 불순물도핑 영역 및 농도에 따른 소자의 특성해석은 LDD구조를 가진 LDMOS가 hot-carrier resistance 및 전력소모 관점에서 우수한 특성을 나타낼 것으로 사료된다

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.11
• /
• pp.49-54
• /
• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.12
• /
• pp.53-58
• /
• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.