• Journal of KIISE:Information Networking
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• v.27 no.4
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• pp.507-521
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• 2000

실시간 멀티미디어 서비스에서 Quality of Service(QoS) 보장의 필요성이 증가하고 있다. 멀티미디어 서비스 제공 형태의 대다수가 될 멀티캐스트 경로설정에서도 QoS 보장은 확장성 신뢰성과 함께 매우 중요한 문제이다. QoS 기반 코어 선택 알고리즘을 제안한다. 제안 알고리즈믄 멀티캐스트 경로설정에서 코어 선택시에 다중 QoS 제약조건을 고려한다. QoS 제약조건은 최소보장 대역폭, 종단 지연, 종단 지연변이 등으로 정의한다. 모의 실험결과는 제안한 QCSA와 Maximum Centered Tree(MCT) Average Centered Tree (ACT) Initial Delay-Constrained Shared Tree(Dcinitial) Random Tree(Random)등의 기존 코어 선택 알고리즘의 성능을 각 항목별로 비교한다 멀티캐스트 그룹 멤버수와 QoS 제약조건을 인자로 한 모의 실험 결과는 제안한 QoS 기반 코어 선택 알고리즘이 기존 코어 선택 알고리즘에 비해서 다중 QoS 제약조건 보장 코어 선택 성공률에서 성능 개선 효과를 가짐을 보여준다. 제안 알고리즘이 본 논문에서 설정한 모의 실험 환경에서는 QoS 기반 코어 선택의 정도를 나타내는 성공률에서 약 10% 정도 기존 알고리즘보다 우수함을 보인다. 이 결과는 제안 알고리즘이 코어 선택 과정의 초기부터 멀티캐스트 그룹내의 모든 멤버에 대한 다중 QoS 제약조건을 고려하는 점이 QoS 기반 코어 선택에서 개선 효과를 나타냄을 보여준다.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.33-35
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• 2012

개인용 컴퓨터가 보급된 후 오랫동안 CPU의 발전은 주로 클럭 스피드를 통해서 이루어져 왔다. 하지만 최근 들어서는 CPU 내에서 동작하는 코어의 수를 늘리는 방법을 통해 CPU의 성능 향상이 이루어지고 있다. 이렇게 멀티코어 환경의 시대가 도래함에 따라 CPU를 완전하게 이용하기 위해 기존 알고리즘들의 병렬화가 필요로 하게 되었다. 본 논문에서는 가장 많이 사용되는 알고리즘의 종류 중 하나인 정렬 알고리즘을 병렬화하여 멀티 코어 환경에서의 성능을 평가한다. 이는 기존의 단일 스레드 정렬 알고리즘들에 대해 알려진 바와는 다른 경향을 보이며 이러한 현상은 CPU의 병렬화가 진행될수록 더욱 심화될 것으로 예상된다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.9
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• pp.1-10
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• 2013

In this paper, we implement the SIFT(Scale-Invariant Feature Transform) algorithm for feature point extraction using a many-core processor, and analyze the performance, area efficiency, and system area efficiency of the many-core processor. In addition, we demonstrate the potential of the proposed many-core processor by comparing the performance of the many-core processor with that of high-performance CPU and GPU(Graphics Processing Unit). Experimental results indicate that the accuracy result of the SIFT algorithm using the many-core processor was same as that of OpenCV. In addition, the many-core processor outperforms CPU and GPU in terms of execution time. Moreover, this paper proposed an optimal model of the SIFT algorithm on the many-core processor by analyzing energy efficiency and area efficiency for different octave sizes.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.171-181
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• 2012

This paper defines the AES password algorithm used as a symmetric-key-based password algorithm, and proposes the design of parallel password algorithm to utilize the resources of multi-core processor as much as possible. The proposed parallel password algorithm was confirmed for parallel execution of password computation by allocating the password algorithm according to the number of cores, and about 30% of performance increase compared to AES password algorithm. The encryption/decryption performance of the password algorithm was confirmed through binary comparative analysis tool, which confirmed that the binary results were the same for AES password algorithm and proposed parallel password algorithm, and the decrypted binary were also the same. The parallel password algorithm for multi-core environment proposed in this paper can be applied to authentication/payment of financial service in PC, laptop, server, and mobile environment, and can be utilized in the area that required high-speed encryption operation of large-sized data.

• Journal of IKEEE
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• v.16 no.4
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• pp.375-381
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• 2012

In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.174-177
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• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Journal of KIISE
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• v.44 no.5
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• pp.469-475
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• 2017

The emerging NVMe-based multi-queue SSDs provides a high bandwidth by parallel I/O, i.e., each core performs I/O through its dedicated queue in parallel with other cores. To provide a bandwidth share for each application with I/O, a fair-share scheduler that provides a bandwidth share to each core is required. In this study, we proposed a multi-core scalable fair-queuing algorithm for multi-queue SSDs. The algorithm adopts randomization to minimize the inter-core synchronization overheads and provides a weight-proportional bandwidth share to each core. The results of our experiments indicated that the proposed algorithm gives accurate bandwidth partitioning and outperforms the existing FlashFQ scheduler, regardless of the number of cores for a Linux kernel with block-mq.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.117-123
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• 2008

In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.

• Journal of the Korea Society of Computer and Information
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• v.19 no.9
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• pp.21-31
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• 2014

Singular value decomposition (SVD) has been widely used to identify unique features from a data set in various fields. However, a complex matrix calculation of SVD requires tremendous computation time. This paper improves the performance of a representative one-sided block Jacoby algorithm using a two-dimensional (2D) multi-core system. In addition, this paper explores an optimal multi-core system by varying the number of processing elements in the 2D multi-core system with the same 400MHz clock frequency and TSMC 28nm technology for each matrix-based one-sided block Jacoby algorithm ($128{\times}128$, $64{\times}64$, $32{\times}32$, $16{\times}16$). Moreover, this paper demonstrates the potential of the 2D multi-core system for the one-sided block Jacoby algorithm by comparing the performance of the multi-core system with a commercial high-performance graphics processing unit (GPU).