• 제목/요약/키워드: Junction Device

검색결과 426건 처리시간 0.027초

Photoconductive Atomic Force Microscopy를 이용한 빛의 세기 및 파장의 변화에 따른 폴리실리콘 태양전지의 광전특성 분석 (Characterization of Light Effect on Photovoltaic Property of Poly-Si Solar Cell by Using Photoconductive Atomic Force Microscopy)

  • 허진희
    • 한국재료학회지
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    • 제28권11호
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    • pp.680-684
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    • 2018
  • We investigate the effect of light intensity and wavelength of a solar cell device using photoconductive atomic force microscopy(PC-AFM). A $POCl_3$ diffusion doping process is used to produce a p-n junction solar cell device based on a polySi wafer, and the electrical properties of prepared solar cells are measured using a solar cell simulator system. The measured open circuit voltage($V_{oc}$) is 0.59 V and the short circuit current($I_{sc}$) is 48.5 mA. Moreover, the values of the fill factors and efficiencies of the devices are 0.7 and approximately 13.6 %, respectively. In addition, PC-AFM, a recent notable method for nano-scale characterization of photovoltaic elements, is used for direct measurements of photoelectric characteristics in limited areas instead of large areas. The effects of changes in the intensity and wavelength of light shining on the element on the photoelectric characteristics are observed. Results obtained through PC-AFM are compared with the electric/optical characteristics data obtained through a solar simulator. The voltage($V_{PC-AFM}$) at which the current is 0 A in the I-V characteristic curves increases sharply up to $18W/m^2$, peaking and slowly falling as light intensity increases. Here, $V_{PC-AFM}$ at $18W/m^2$ is 0.29 V, which corresponds to 59 % of the average $V_{oc}$ value, as measured with the solar simulator. Furthermore, while the light wavelength increases from 300 nm to 1,100 nm, the external quantum efficiency(EQE) and results from PC-AFM show similar trends at the macro scale but reveal different results in several sections, indicating the need for detailed analysis and improvement in the future.

4H-SiC UMOSFET의 gate dielectric 물질에 따른 온도 신뢰성 분석 (Temperature reliability analysis according to the gate dielectric material of 4H-SiC UMOSFET)

  • 정항산;허동범;김광수
    • 전기전자학회논문지
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    • 제25권1호
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    • pp.1-9
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    • 2021
  • 본 논문에서는 고전압, 고전류 동작에 적합한 4H-SiC UMOSFET에 대해서 연구하였다. 일반적으로 SiO2는 SiC MOSFET에서 gate dielectric으로 가장 많이 사용되는 물질이다. 하지만 4H-SiC보다 유전 상수 값이 2.5배 낮아서 높은 전계를 갖게 되므로 SiO2/SiC 접합 부분에서 열악한 특성을 갖는다. 따라서 high-k 물질을 gate dielectric으로 적용한 소자를 SiO2를 적용한 소자와 TCAD 시뮬레이션을 통해 전기적 특성을 비교하였다. 그 결과 BV 감소, VTH 감소, gm 증가, Ron 감소를 확인하였다. 특히 온도가 300K일 때, Al2O3와 HfO2의 Ron은 66.29%, 69.49%가 감소하였으며 600K일 때도 39.71%, 49.88%가 감소하였다. 따라서 Al2O3와 HfO2가 고전압 SiC MOSFET의 gate dielectric 물질로써 적합함을 확인하였다.

비차폐 환경에서의 고온초전도 SQUID 2차 미분기의 특성연구 (High-$T_c$ 2nd-order SQUID Gradiometer for Use in Unshielded Environments)

  • 박승문;강찬석;이순걸;유권규;김인선;박용기
    • Progress in Superconductivity
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    • 제5권1호
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    • pp.50-54
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    • 2003
  • We have fabricated $∂^2$$B_{z}$ /$∂x^2$ type planar gradiometers and studied their properties in operation under various field conditions. $YBa_2$$Cu_3$$O_{7}$ film was deposited on $SrTiO_3$ (100) substrate by a pulsed laser deposition (PLD) system and patterned into a device by the photolithography with ion milling technique. The device consists of 3 pickup loops designed symmetrically Inner dimension and the width of the square side loops are 3.6 mm and 1.2 mm, respectively, and the corresponding dimensions of the center loop are 2.0 mm and 1.13 mm. The length of baseline gradiometer is 5.8 mm. Step-edge junction width is 3.0 $\mu\textrm{m}$ and the hole size of the SQUID loop is 3 $\mu\textrm{m}$ ${\times}$ 52 $\mu\textrm{m}$. The SQUID inductance is estimated to be 35 pH. The device was formed on a 20 mm ${\times}$ 10 mm substrate. We have tested the behavior of the device in various field conditions. The unshielded gradiometer was stable under extremely hostile conditions on a laboratory bench. Noise level 0.45 pT/$\textrm{cm}^2$/(equation omitted)Hz and 0.84 pT/$\textrm{cm}^2$/(equation omitted)Hz at 1 Hz for the shielded and the unshielded cases, which correspond to equivalent field noises of 150 fT/(equation omitted)Hz and 280 fT/(equation omitted)Hz, respectively. In spite of the short baseline of 5.8 mm, the high common-mode-rejection-ratio of the gradiometer, $10^3$, allowed us to successfully record magnetocardiogram of a human subject, which demonstrates the feasibility of the design in biomagnetic studies.

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THE EFFECT OF DOPANT OUTDIFFUSION ON THE NEUTRAL BASE RECOMBINATION CURRENT IN Si/SiGe/Si HETEROJUNCTION BIPOLAR TRANSISTORS

  • Ryum, Byung-R.;Kim, Sung-Ihl
    • ETRI Journal
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    • 제15권3_4호
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    • pp.61-69
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    • 1994
  • A new analytical model for the base current of Si/SiGe/Si heterojunction bipolar transistors(HBTs) has been developed. This model includes the hole injection current from the base to the emitter, and the recombination components in the space charge region(SCR) and the neutral base. Distinctly different from other models, this model includes the following effects on each base current component by using the boundary condition of the excess minority carrier concentration at SCR boundaries: the first is the effect of the parasitic potential barrier which is formed at the Si/SiGe collector-base heterojunction due to the dopant outdiffusion from the SiGe base to the adjacent Si collector, and the second is the Ge composition grading effect. The effectiveness of this model is confirmed by comparing the calculated result with the measured plot of the base current vs. the collector-base bias voltage for the ungraded HBT. The decreasing base current with the increasing the collector-base reverse bias voltage is successfully explained by this model without assuming the short-lifetime region close to the SiGe/Si collector-base junction, where a complete absence of dislocations is confirmed by transmission electron microscopy (TEM)[1].The recombination component in the neutral base region is shown to dominate other components even for HBTs with a thin base, due to the increased carrier storage in the vicinity of the parasitic potential barrier at collector-base heterojunction.

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Monolithic SiGe Up-/Down-Conversion Mixers with Active Baluns

  • Lee, Sang-Heung;Lee, Seung-Yun;Bae, Hyun-Cheol;Lee, Ja-Yol;Kim, Sang-Hoon;Kim, Bo-Woo;Kang, Jin-Yeong
    • ETRI Journal
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    • 제27권5호
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    • pp.569-578
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    • 2005
  • The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

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LDD NMOSFET의 Metallurgical 게이트 채널길이 추출 방법 (The Extraction Method of LDD NMOSFET's Metallurgical Gate Channel Length)

  • 조명석
    • 전기전자학회논문지
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    • 제3권1호
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    • pp.118-125
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    • 1999
  • 게이트 아래의 기판과 쏘오스/드레인의 접합부분 사이의 길이로 정의되는 LDD MOSFET의 metallurgical 채널 길이를 커패시턴스 측정을 이용하여 결정할 수 있는 방법을 제안하였다. 전체의 게이트 면적이 동일한 평판 모양과 손가락 모양의 LDD MOSFET 게이트 테스트 패턴의 커패시턴스를 측정하였다. 각 테스트 패턴의 쏘오스/드레인과 기판의 전압을 접지시키고 게이트의 전압을 변화시키면서 커페시턴스를 측정하였다. 두 테스트 패턴의 측정치의 차이를 그려서 최대점이 나타나는 점의 값를 간단한 수식에 대입하여 metallurgical 채널 길이를 구하였다. 이차원적 소자 시뮬레이터를 사용하여 수치해석적 모의 실험을 함으로써 제안한 방법을 증명하였다.

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C-Band 위성통신용 고출력 증폭기의 설계 및 제작 (A Design and Fabrication of a High Power SSPA for C-Band Satellite Communication)

  • 예성혁;윤순경;전형준;나극환
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 1996년도 학술대회
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    • pp.27-31
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    • 1996
  • In this paper, The SSPA(Solid State Power Amplifier) is 100 watts amplifier which is used with C-Band Satellite communication Up-Link frequency, 5.875 ∼6.425 GHz. SSPA requires more output power than is available from a single GaAs FET with result it is necessary to combine the output of many device. To achieve a high power, it is important to make a good N-way power divider which has a small different phase, good combining efficiency and high power handling capability. The reliability of Power GaAs FET decrease with increasing junction temperature, power amplifier in general dissipate amount of power. It is important to provide them with a heatsink and a temperature compensation circuit to dispose of the unwanted heat. To compensate temperature, Using PIN diode attenuator, it is enable to get a precision gain control. The output power of the SSPA is more than 100 watt with which the TWTA (Traveling-Wave Tube Amplifier) can be replaced. Each stage was measured by the Network analyzer PH8510C, Power meter Booton 42BD, The gain is more than 53 dB, flatness is less than 1.5 dB.

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고주파 및 고전력 인버터 적용을 위한 Half-Bridge SIT의 병렬운전 특성고찰 (Parallel Operation of a Pair of SITs in order to raise the High Frequency and Power Half-Bridge Inverter)

  • 최상원;김진표;이종하
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 하계학술대회 논문집 F
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    • pp.2234-2236
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    • 1997
  • The SIT, a Static Induction Transistor, is a semiconductor switch that is also called the power junction field-effect transistor (power JFET). Its characteristics are similar to a MOSFET except that its power level is higher and its maximum frequency of operation is lower. The normal method to protect against internal circuit transients of the form of di/dt or dv/dt is the use of snubber circuits. However, the limits of di/dt and dv/dt are high enough for the SIT that it is possible to operate without snubber circuits. SITs can be connected in parallel in order to cope with higher load currents that the value of an individual device rating. The purpose of this study is to investigate the parallel operation of SITs. In this experiment, we used a half-bridge inverter, the output of inverter is up to almost 1MHz and 2kW. Experimental results show that the operation of parallel connected SITs are facilitated individually good current sharing. The reason is the positive temperature coefficient of resistance of the SIT.

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A semispherical SQUID magnetometer system using high sensitivity double relaxation oscillation SQUIDs for magnetoencephalographic measurements

  • Lee, Yong-Ho;Hyukchan Kwon;Kim, Jin-Mok;Kim, Kwoong;Park, Yong-Ki
    • 한국초전도ㆍ저온공학회논문지
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    • 제5권1호
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    • pp.21-26
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    • 2003
  • We designed and constructed a multichannel superconducting quantum interference device (SQUID) magnetometer system to measure magnetic fields from the human brain. We used a new type of SQUID, the double relaxation oscillation SQUID (DROS). With high flux-to-voltage transfers of the DROS, about 10 times larger than the dc SQUIDs, simple flux-locked loop circuits could be used for SQUID operation. Also the large modulation voltage of the DROS, typically being 100 $mutextrm{V}$, enabled stable flux-locked loop operation against the thermal offset voltage drift of the preamplifier. The magnetometers were fabricated using the Nb/AlOx/Nb junction technology. The SQUID system consists of 37 signal magnetometers, distributed on a semispherical surface, and 11 reference channels were installed to pickup background noises. External feedback was used to eliminate the magnetic coupling with the adjacent channels. The liquid helium dewar has a capacity of 29 L and boil-off rate of about 4 L/d with the total 48 channel insert. The magnetometer system has an average noise level of 3 fT/√Hz at 100 Hz, inside a shielded loon, and was applied to measure auditory-evoked fields.

외부 전계 링을 갖는 LDMOST의 항복전압 특성 (Breakdown Voltage Characteristics of LDMOST with External Field Ring)

  • 오동주;염기수
    • 한국정보통신학회논문지
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    • 제8권8호
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    • pp.1719-1724
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    • 2004
  • 본 논문에서는 차세대 RF 전력 소자로 기대하고 있는 LDMOST의 BV(Breakdown; 항복전압) 특성을 향상시키는 새로운 구조를 제안하였다. 제안한 구조는 외부 전계 링이라 하며 드리프트 영역 둘레에 3차원적인 구조로 형성된다. 외부 전계 링은 드리프트 영역에서 전계를 완화시키는 역할을 함으로써 BV 특성을 향상시키는 효과를 얻을 수 있다. 3차원 TCAD 시뮬레이션 결과, 외부 전계 링의 접합깊이와 도핑 농도의 증가에 따라 LDMOST의 BV가 증가함을 확인할 수 있었다. 따라서 기존의 p+ sinker 공정을 사용하여 외부 전계 링 구조를 추가한다면 LDMOST의 BV 특성을 크게 향상 시킬 수 있다.