• 수산해양교육연구
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• 제23권2호
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• pp.162-181
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• 2011

The purpose of this study was to reveal controversial issues on Stages of Concern(SoC), which is one of the dimensions of Concerns Based Adoption Model(CBAM). To achieve the purpose, documental analysis was employed. The theoretical framework to analyze literature consisted of three categories including stages, measurements, and applications. Based on the framework, controversial issues on SoC were discussed regarding arguments of CBAM developers and critics. The researchers of this study suggested their own opinions on the issues after thorough examination of CBAM developer's arguments and oppositions against them. Finally, suggestions for further studies on issues of SoC and studies measuring SoC were made.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• 전자통신동향분석
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• 제33권6호
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• pp.24-33
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• 2018

In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.

• 한국정보통신학회논문지
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• 제10권1호
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• pp.57-64
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• 2006

다중처리기 SoC(System on Chip) 플랫폼은 SoC 설계를 위한 새로운 혁신적인 경향들을 가지고 있다. QoS 인수와 성능 매트릭스는 SoC을 위한 새로운 설계 방법론을 채택하도록 하였다. 이것은 NOC의 하부 통신 백본뿐만 아니라 전체 시스템 구조가 고도로 확장가능하고, 재사용가능하고, 예측가능하면서 가격과 에너지 측면에서 효율적인 플랫폼이 되도록 구체화할 것이다. 우리는 NOC의 통신 백본 구조가 계층화된 것처럼 NOC의 전체 시스템 구조가 자체적으로 7 계층이 되도록 제안한다. 이런 플랫폼은 동기화 문제를 가지는 병행성을 보다 효과적으로 모델화하는 영역에 특수한 문제들을 분리할 수 있다. 그러한 계층 구조에서 계산 모델은 어떤 응용에 자연스러운 병행성과 동기화 문제를 모형 할 수 있는 뼈대를 제공할 것이다. 그러므로 특정 NOC 영역에서 올바른 계산 모델을 사용하는 것은 아주 중요하다.

• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of information and communication convergence engineering
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• 제6권4호
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• 한국군사과학기술학회지
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• 제25권5호
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• pp.513-521
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• 2022

This study deals with an AI architecture model for collecting battlefield data using the tactical C4I system. Based on this model, the artificial staff can be utilized in tactical echelon. In the current structure of the Army's tactical C4I system, Servers are operated by brigade level and above and divided into an active and a standby server. In this C4I system structure, the AI server must also be installed in each unit and must be switched when the C4I server is switched. The tactical C4I system operates a server(DB) for each unit, so data matching is partially delayed or some data is not matched in the inter-working process between servers. To solve these issues, this study presents an operation concept so that all of alternate server can be integrated based on virtualization technology, which is used as an source data for AI Meta DB. In doing so, this study can provide criteria for the AI architectural model of the ground tactical echelon.

• 대한전자공학회논문지SD
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• 제45권1호
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• pp.14-19
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• 2008

현대 반도체의 소형화 및 고성능화로 인해 반도체 테스팅 분야는 다양한 문제점에 봉착하고 있다. 이중 연결선에 대한 signal integrity 문제는 SoC와 같은 고집적 회로에서 반드시 해결해야할 문제이다. 본 논문에서는 연결선의 signal integrity 테스트를 위한 효과적인 테스트 패턴 적용 방안을 제안한다. 제안하는 테스트 패턴은 경계 주사 구조를 통해 적용 가능하며, 상당히 짧은 테스트 시간으로 매우 효과적인 테스트를 수행할 수 있다.

• 대한전자공학회논문지SD
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• 제43권1호
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• pp.71-78
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• 2006

NoC 테스트는 온칩네트워크를 TAM으로 재사용하기 때문에 SoC 구조 기반의 여러 테스트 기법을 그대로 사용할 수가 없다. 본 논문에서는 네트워크 기반 TAM의 문제점을 크게 감소시킨 새로운 형태의 NoC 테스트 플랫폼을 소개하며 이를 이용한 NoC 테스트 스케줄링 알고리즘을 제안한다. 제안한 알고리즘은 SoC 테스트 용도로 개발된 rectangle packing 방식을 기반으로 효율적이고 체계적인 테스트 스케줄링이 가능하게 한다. ITC'02 벤치회로를 이용한 실험 결과 제안한 방법이 기존 방법에 비해 최대 $55\%$까지 테스트 시간을 줄일 수 있음을 확인하였다.