• Journal of Fisheries and Marine Sciences Education
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• v.23 no.2
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• pp.162-181
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• 2011

The purpose of this study was to reveal controversial issues on Stages of Concern(SoC), which is one of the dimensions of Concerns Based Adoption Model(CBAM). To achieve the purpose, documental analysis was employed. The theoretical framework to analyze literature consisted of three categories including stages, measurements, and applications. Based on the framework, controversial issues on SoC were discussed regarding arguments of CBAM developers and critics. The researchers of this study suggested their own opinions on the issues after thorough examination of CBAM developer's arguments and oppositions against them. Finally, suggestions for further studies on issues of SoC and studies measuring SoC were made.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.24-33
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• 2018

In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.57-64
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• 2006

Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.5
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• pp.513-521
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• 2022

This study deals with an AI architecture model for collecting battlefield data using the tactical C4I system. Based on this model, the artificial staff can be utilized in tactical echelon. In the current structure of the Army's tactical C4I system, Servers are operated by brigade level and above and divided into an active and a standby server. In this C4I system structure, the AI server must also be installed in each unit and must be switched when the C4I server is switched. The tactical C4I system operates a server(DB) for each unit, so data matching is partially delayed or some data is not matched in the inter-working process between servers. To solve these issues, this study presents an operation concept so that all of alternate server can be integrated based on virtualization technology, which is used as an source data for AI Meta DB. In doing so, this study can provide criteria for the AI architectural model of the ground tactical echelon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.14-19
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• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.71-78
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• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.