• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.20-26
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• 1993

The base-collector capacitance of an npn bipolar transistor in bipolar or BiCMOS technology has significant influence on the switching performances, and comprises pnjunction component and MOS component. Both components have complicated dependences on the isolation oxide structure, epitaxial doping density, and bias voltage. Analytical/empirical formulas for both components are derived in this paper for a generic isolation structure as a function of epitaxial doping density and bias voltage based on some theoretical understanding and two-dimensional device simulations. These formulas are useful in estimating the effect of device isoation schemes on the switching speed of bipolar transistors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.249-252
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog to comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an exective isolation strategy for removing noise and signal coupling of each sensor pixel. The 128$\times$144 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of Power Electronics
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• v.17 no.1
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• pp.305-313
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• 2017

A novel interference isolation method is proposed by using several designed coils in capacitive power transfer systems as isolation impedances. For each designed coil, its stray parameters such as the inter-turn capacitance, coil resistance and capacitance between the coil and the core, etc. are taken into account. An equivalent circuit model of the designed coil is established. According to this equivalent circuit, the impedance characteristic of the coil is calculated. In addition, the maximum impedance point and the corresponding excitation frequency of the coil are obtained. Based on this analysis, six designed coils are adopted to isolate the interference from power delivery. The proposed method is verified through experiments with a power carrier frequency of 1MHz and a data carrier frequency of 8.7MHz. The power and data are transferred parrallelly with a data carrier attenuation lower than -5dB and a power attenuation on the sensing resistor higher than -45dB.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.4
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• pp.178-184
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• 2005

In this paper, using diplexer structure and varactor diode controlled by reverse bias voltage for diplexer switch gives possibilities to improve isolation and current characteristics. 1 have newly designed switch with high isolation by application varactor diode corresponding to capacitor of diplexer. The low-pass filter for proposed tunable diplexer passes the microwave signal in the bandwidth for wireless cellular network systems and high-pass filter passes it in the bandwidth for wireless personal communication services (PCS) network systems. As the capacitance of the low-pass filter increases, the cut-off frequency can be moved to low frequency, so that the switch is on state in cellular bandwidth and off state in the PCS bandwidth, in contrast to, as the capacitance for attenuation characteristic of high-pass filter increases, it can be moved to high frequency, so that the switch is off state and on state in the cellular bandwidth. it is possible to improve isolation and current consumption characteristics by application diplexer design methods and varactor diode. 1 expect that the tunable diplexer circuit and design methods should be able to find applications on MMIC and low temperature copired ceramic (LTCC).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1297-1303
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.167-173
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• 2005

The isolation of the series PIN diode switch is restricted by the parallel capacitance of PIN diode and the switch driver circuit limits switching speed of PIN diode switch. To overcome these problems, a high isolation and high switching speed Pin diode switch is proposed adapting the parallel resonant inductance and TTL compatible switch driver circuit. The measurement results of the 3 GHz PM diode switch show 1 GHz frequency band, less than 1.5 dB insertion loss, 65 dB isolation, more than 15 dB return loss and less than 30 ns switching speed. In particular the 3 GHz PIN diode switch using the parallel resonant inductance exhibits the improvement of isolation by 15 dB.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.949-954
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• 2012

The K-PCS and W-CDMA dual band dielectric duplexer and bandpass filters have been designed and fabricated. The dual band duplexer consists of the separate monoblock K-PCS and W-CDMA duplexers using common antenna port. The coupling capacitance and I/O impedance matching have been designed to minimize the cross interference between the bands. Isolations of crosspoint between Tx and Rx in K-PCS and W-CDMA dualband were about 47 dB and 100 dB, respectively. On the other hand, isolations of Tx and Rx in K-PCS and W-CDMA were about 66 dB and 65 dB, respectively. The difference between 47 dB and 100 dB originated from the different center frequencies in Tx and Rx of K-PCS and W-CDMA bands. The coupling capacitance of the bandwidth, I/O capacitance of I/O matching and impedance matching, and various capacitances were important role to fabricate the dielectric duplexer and bandpass filters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.33-41
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• 2003

In this work, process optimization techniques for high frequency performance of HBTs are presented. The techniques are focused on reducing parasitic base resistance and base-collector capacitance, which are key elements determining the high frequency characteristics of HBTs. Several fabrication techniques, which can significantly reduce the parasitic elements of the HBTs for improved high frequency performance, are proposed and verified by the measured data of the fabricated devices.