• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.305-311
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• 2013

This paper proposes a performance improvement of existing single-phase current-fed qZ-Source inverter. Voltage gain of the traditional voltage-fed full-bridge inverter and single-phase current-fed qZ-source inverter is only equal to or smaller than input voltage. The proposed inverter can obtain twice higher voltage gain than the single-phase current-fed qZ-Source inverter by adding an extra switch and a capacitor in the circuit. In addition, the proposed inverter shares the common ground between dc input and ac output voltage. Therefore, the proposed inverter can eliminate the possible ground leakage current problem when it is used for grid-tied photovoltaic inverter system. A 120 W prototype inverter is built and tested to verify performances of the proposed inverter.

• Journal of Power Electronics
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• v.14 no.5
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• pp.918-925
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• 2014

This study presents an extended boost single-phase qZ-source DC-AC inverter for a single-phase photovoltaic system. Unlike the previously proposed single-phase qZ-source and semi-qZ-source inverters that achieve the same output voltage as that of the traditional voltage-fed full-bridge inverter, the proposed inverter can obtain higher output than input voltage. The proposed inverter also shares a common ground between DC input voltage and AC output voltage. Thus, possible ground leakage current problem in non-isolated grid-tied inverters can be eliminated with the proposed inverter. A 120 W prototype inverter is built and tested to verify the performance of the proposed inverter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.9-12
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• 1998

In this paper, the power factor correction circuit using a parallel drive method is proposed so that the high power inverter air-conditioner with 3[ph] compressor motor may obtain the cost down and the improved performance. The adequate design procedures are presented to reduce the material costs by eliminating the power factor improving LC filter and derating output capacitor and inverter switches. Using the determined components, the prototype circuit with 6[kW] power consumption is built and tested to verify the operation of the proposed circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.58-69
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• 2016

This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.

• Journal of Power Electronics
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• v.18 no.1
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• pp.277-288
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• 2018

Wireless inductive power transfer (IPT) technology is used in many applications today. A compact and high-frequency primary side inverter is one of the most important parts of a WPT system. In this study, a modified class EF-type voltage-fed multi-resonant inverter has been proposed for WPT application at a frequency range of 85-100 kHz. Instead of an infinite input choke inductor, a resonant inductor is used to reduce loss and power density. The peak voltage stress across the MOSFET has been reduced to almost 60% from a class-E inverter using a passive clamping circuit. A simple yet effective design procedure has been presented to calculate the various component values of the proposed inverter. The overall system is simulated using MATLAB/SimPowerSystem to verify the theoretical concepts. A 500-W prototype was built and tested to validate the simulated results. The inverter exhibited 90% efficiency at nearly perfect alignment condition, and efficiency reduced gradually with the misalignment of WPT coils. The proposed inverter maintains zero-voltage switching (ZVS) during considerable load changes and possesses all the inherent advantages of class E-type inverters.

• Journal of Power Electronics
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• v.14 no.2
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• Journal of Power Electronics
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• v.17 no.1
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• pp.115-126
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• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.275-278
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• 2003

Conventional vector control inverter is usually used for blower of air-accord equipment. In this paper, it is proposed that inverter is controlled by instantaneous following PWM controller. This controller compensate and follow for output voltage of inverter within one switching cycle as an error that compared output voltage of rectifier included much ripples with reference voltage of sine wave. It has not speedy response like vector controller, but the circuit is very simple as using analog integer. And it has advantages that develop input power factor, built small-capacity and low-cost because huge capacitor of voltage type inverter removed.

• Journal of Power Electronics
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• v.11 no.1
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• pp.74-81
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• 2011

The cutoff frequency of the output LC filters of PWM inverters limits the control bandwidth of the converter system while it attenuates voltage ripples that are caused by inverter switching activities. For a selected cutoff frequency of an output LC filter, an infinite number of L-C combinations is possible. This paper analyses the characteristics of output LC filters for PWM inverters terms of the L-C combinations. Practical circuit conditions such as no-loads, full resistive-loads, and inductive-load conditions are considered in the analysis. This paper proposes a LC filter design method for PWM inverters considering both the voltage ynamics and he inverter stack size. An experimental PWM inverter system based on the proposed output LC lter design uideline is built and tested.