• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.58-58
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• 2000

As many sensors and actuators are used in various automated systems, the application of network system to real-time distributed control is gaining acceptance in many industries. In order to take advantages of the network technique. however, network implementation should be carefully designed to satisfy real-time constraints and to consider network delays. This paper presents the implementation of feedback control system in Profibus-DP. Profibus-DP is a type of fieldbus protocols that are specifically designed to interconnect simple devices with fast I/O data exchange. As feedback control in profibus-DP is implemented, Network delays is found with influence of system performance. We analyze network delays in Profibus-DP into 3 reasons - dead time in Profibus interface, protocol delay, delay by asynchronization. In order to compensate the network delays, we introduce control algorithms with time delay concept. The results show that network delay can be compensated.

• 대한전자공학회논문지SD
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• 제48권3호
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• pp.25-33
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• 2011

Chip 동작 주파수가 상승함에 따라, 온-칩 인터커넥에서 인덕턴스 문제 대한 우려가 증가하고 있다. 본 논문에서는 VLSI 설계에서 인덕턴스 효과가 큰 인터커넥을 선택하는 2단계의 인덕턴스 screening tool을 소개한다. Technology가 scaling함에 따라 인터커넥의 단면이 줄어들어 저항이 증가한다. 저항의 증가는 인덕턴스의 영향을 줄이는 효과가 있다. 따라서 각각 다른 CMOS 공정(0.25${\mu}m$, 0.13${\mu}m$, 90nm)을 사용하여 디자인된 칩을 개발한 tool로 실험함으로써 technology scaling에 따른 인덕턴스 영향을 분석해 보았다. 인덕턴스 screening tool의 결과는 디자인의 0.1% 이내의 net들이 작동 주파수에서 인덕턴스 문제를 보임으로써, 모든 인터커넥에 인덕턴스 모델을 추가하는 대신 인덕턴스 screening을 한 후 필요한 인터커넥에만 추가하는 것이 효율적임을 알 수 있다. 대부분 test chip들이 본래 칩 동작 주파수에서는 인덕턴스 영향이 문제되지 않았지만, 주파수를 높일 경우 문제가 되는 인터커넥들을 찾아낼 수 있었다. 본 연구에서 개발한 인덕턴스 screening tool은 회로 설계자들에게 유용한 지침을 제공할 수 있을 것이다.

• 전자공학회논문지C
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• 제35C권4호
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.603-605
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• 1998

In recent years, chip delay estimation has had an increasingly important impact on overall design technology. The analysis of the timing behavior of an ASIC should be based not only on the delay characteristics of gates and interconnect circuits but also on the interactions between them. This model plays an important role in our CAD system to analyze the ASIC timing characteristics accurately, together with two-dimensional gate delay table model, AWE algorithm and effective capacitance concept. In this paper, we present an efficient algorithm which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC-tree and an effective capacitance equation that captures the complete waveform response accurately.

• 마이크로전자및패키징학회지
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• 제25권4호
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• pp.1-7
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• 2018

As the performance and density of IC (integrated circuit) devices increase, power and signal integrities in the global interconnects of advanced packaging technologies are becoming more difficult. Thus, the global interconnect technologies should be designed to accommodate increased input/output (I/O) counts, improved power grid network integrity, reduced RC delay, and improved electrical crosstalk stability. This requirement resulted in the fine-pitch interconnects with a low-k dielectric in 3D packaging or wafer level packaging structure. This paper reviews an organic-inorganic hybrid material as a potential dielectric candidate for the global interconnects. An organic-inorganic hybrid material called polysiloxane can provide spin process without high temperature curing, an excellent dielectric constant, and good mechanical properties.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 대한전자공학회논문지SD
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• 제42권5호
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• pp.39-46
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• 2005

본 논문은 SoC 상에서 정적인 고장 뿐 아니라 동적인 고장도 점검하고 진단할 수 있는 새로운 At-speed Interconnect Test Controller (ASITC)를 소개한다. SoC는 IEEE 1149.1과 P1500 래퍼의 코아들로 구성되고 다중 시스템 클럭에 의해 동작될 수 있으며, 이러한 복잡한 SoC를 테스트하기 위해 P1500 래퍼의 코아를 위한 인터페이스 모듈과 update부터 capture까지 1 시스템 클럭으로 연결선의 지연 고장을 점검할 수 있는 ASITC를 설계하였다. 제안한 ASITC는 FPGA로 구현하여 기능검증을 하였으며 기존의 방식에 비해 테스트 방법이 쉽고, 면적의 오버헤드가 적다는 장점이 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• 전자공학회논문지A
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• 제32A권12호
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• pp.209-219
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• 1995

As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2007년도 가을 학술발표논문집 Vol.34 No.2 (B)
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• pp.264-268
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• 2007

연결선(interconnect) 사이의 간섭으로 발생하는 crosstalk 지연시간(delay)을 제거하기 위한 두 가지의 방법을 제안 한다. (1) 체계적인 코드를 생성해내는 방법으로 crosstalk 지연시간(delay) 유발 경우를 두 가지의 종류로 분류하여 각각에 대해 버스(bus) 비트 수의 증가에 따른 analytic 한 코드 생성 공식을 유도하였다; (2) 부-버스(sub-bus) 간에 발생하는 crosstalk 지연시간(delay)을 기존의 방법에 비해 보다 효율적으로 제거하는, 즉 추가적인 차단 라인 (또는 complement 비트 라인)를 감소시키는 방법을 제안 한다. 두 연구 결과는 연결선 상의 데이터 전송에 따른 신뢰성, 지연시간 및 전력 소모 증가를 유발하는 crosstalk를 차단하는 엔코딩 기법으로 유용하게 사용될 것으로 보인다.