• 센서학회지
• /
• 제8권5호
• /
• pp.421-426
• /
• 1999

본 논문에서는 반절연성 GaAs(semi-insulating GaAs) 기판위에 $Al_2O_3$ 절연막이 게이트 절연막으로 이용된 공핍형모드 p-채널 GaAs MOSFET (depletion mode p-channel GaAs MOSFET)를 제조하였다. 반절연성 GaAs 기판위에 $1\;{\mu}m$의 GaAs 버퍼층(buffer layer), $4000\;{\AA}$의 p형 GaAs 에피층(epi-layer), $500\;{\AA}$의 AlAs층, 그리고 $50\;{\AA}$의 캡층(cap layer)을 차례로 성장시키고 습식열산화시켰으며, 이를 통하여 AlAs층은 완전히 $Al_2O_3$층으로 산화되었다. 제조된 MOSFET의 I-V, $g_m$, breakdown특성 측정을 통하여 AlAs/GaAs epilayer/S I GaAs 구조의 습식열산화는 공핍형 모드 p-채널 GaAs MOSFET를 구현하기에 적합함을 알 수 있다.

• 한국전기전자재료학회논문지
• /
• 제22권12호
• /
• pp.1063-1066
• /
• 2009

In this study, we fabricated pentacene organic thin film trasistors(OTFTs) which used aluminum oxide as the gate insulator. Aluminum oxide for OTFTs was deposited on glass substrate with a different deposition rate by E-beam evaporation. In case of the deposition rate of $0.1\;{\AA}$, the fabricated aluminum oxide gate insulating OTFT showed a threshold voltage of -1.36 V, an on/off current ratio of $1.9{\times}10^3$ and field effect mobility $0.023\;cm^2/V_s$.

• 한국응용과학기술학회지
• /
• 제19권4호
• /
• pp.335-338
• /
• 2002

A new process for polymeric gate insulator in field-effect transistors was proposed. Fourier transform infrared absorption spectra were measured in order to identify ODPA-ODA polyimide. Its breakdown field and electrical conductivity were measured. All-organic thin-film transistors with a stacked-inverted top-contact structure were fabricated to demonstrate that thermally evaporated polyimide films could be used as a gate insulator. As a result, the transistor performances with evaporated polyimide was similar with spin-coated polyimide. It seems that the mass-productive in-situ solution-free processes for all-organic thin-film transistors are possible by using the proposed method without vacuum breaking.

• 전기학회논문지
• /
• 제66권4호
• /
• pp.721-726
• /
• 2017

We fabricated stretchable thin-film transistors(TFTs) on a polydimethylsiloxane substrate with patterned polyimide island structures by using an amorphous InGaZnO semiconductor and parylene gate insulator. The TFTs exhibited a field- effect mobility of $5cm^2V^{-1}s^{-1}$ and a current on/off ratio of $10^5$ at a relatively low operating voltage. Furthermore, the fabricated transistors showed no noticeable changes in their electrical performance for large strains of up to 50 %.

• 한국진공학회지
• /
• 제21권6호
• /
• pp.354-361
• /
• 2012

유기 메모리 절연막 제작을 위해 일반적으로 사용되어지는 습식법이 아닌 건식법 중 플라즈마 중합법을 이용하였다. 유기 절연 박막으로 사용된 단량체는 Styrene과 MMA을 사용하고, 터널링 박막은 MMA를 사용하며, 메모리 박막은 열기상증착법을 이용한 Au 박막을 사용하였다. 최적화된 소자의 구조는 Au의 메모리층의 두께를 7 nm, Styrene 게이트 절연막의 두께를 400 nm, MMA 터널링 박막의 두께를 30 nm로 증착하여 제작된 부동 게이트형 유기 메모리 소자는 40/-40 V의 double sweep시 27 V의 히스테리시스 전압을 얻을 수 있었다. 이 특성을 기준하여 유기 메모리의 전하 포집 특성을 얻을 수 있었다. 유기 재료 중 MMA 대비 Styrene의 전하 포집 특성이 좋은 것으로 보아 향후 부동 게이트인 Au 박막을 유기 재료인 Styrene으로 대체하여 플렉시블 소자의 가능성을 기대한다.

• 전기전자학회논문지
• /
• 제23권3호
• /
• pp.811-816
• /
• 2019

초고진공 화학기상증착장치(UHV-CVD)에 의해 성장된 실리콘-흡착된 산소(Si-O) 초격자가 실리콘 양자전자소자를 위한 에피택셜 장벽으로 소개되었다. 전류-전압 측정 결과 높은 브레이크다운 전압을 갖는 매우 안정하고 양호한 절연특성을 나타내었다. 에피택셜 성장된 Si-O 초격자는 SOI(silicon on insulator)를 대체할 수 있는 절연층으로도 사용될 수 있음을 보여준다. 이 두꺼운 장벽은 전계효과트랜지스터(FET)의 절연 게이트로 유용하게 사용될 수 있어 FET 위에 또 다른 FET를 제작할 수 있으므로 미래 실리콘계 3차원 집적회로의 궁극적인 목표에 한층 더 다가갈 수 있는 가능성을 보여주는 것이다.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 추계학술대회 논문집
• /
• pp.506-508
• /
• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of information and communication convergence engineering
• /
• 제2권2호
• /
• pp.93-96
• /
• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.181-184
• /
• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
• /
• pp.215-216
• /
• 2000

We fabricated the thin-film transistors using organic semiconductor, pentacene, on $SiN_x$, gate insulator. X-ray diffraction experiments were performed for the sample after heat-treatments at higher temperatures. We confirmed that we obtained "thin-film phase" from the condition used here. From the electrical measurements, we also confirmed that no charges are accumulated at the interface between organic and insulating layer, and FET characteristics of the organic FET using pentacene was discussed.