• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.903-906
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• 2011

The electroplating and electro-less plating methods have been applied for the high density chip interconnect of the Copper Pillar Tin Bump (CPTB) preparation. The CPTB was prepared, which had been electroplated about $100{\mu}m$ pitch of copper layer firstly, and then the Tin layer was deposited on the copper pillar surface to protect the oxidation of it. It was also very important to get uniform thickness of electroplated copper layer, though it was difficult and sensitive. In order to control the thickness distribution, it was examined that the current separating disk of Insulating Gate with a hole in the center was installed between electrodes. The current flows through the center hole of the Insulating Gate in the cylindrical electroplating bath and the other parts were blocked to protect current flowing. The main current flowed through the center hole of the Insulating Gate directly to the opposite electrode of wafer disk. As the results, it was verified that the copper layer was thick in the center part of wafer disk with distribution of thinner to the outer part toward edge.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.286-290
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• 2020

The formation of inorganic thin films in low-temperature solution processes is necessary for a wide range of commercial applications of organic electronic devices. Aluminum oxide thin films can be utilized as barrier films that prevent the deterioration of an electronic device due to moisture and oxygen in the air. In addition, they can be used as the gate insulating layers of a thin film transistor. In this study, aluminum oxide thin film were formed using two methods simultaneously, a thermal process and the DUV process, and the properties of the thin films were compared. The result of converting aluminum nitrate hydrate to aluminum oxide through a hybrid process using a thermal treatment and DUV was confirmed by XPS measurements. A film-based a-IGZO TFT was fabricated using the formed inorganic thin film as a gate insulating film to confirm its properties.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• ETRI Journal
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• v.35 no.6
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• pp.1164-1167
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• 2013

We correlate the failure in miniature X-ray tubes with the field emission gate leakage current of gated carbon nanotube emitters. The miniature X-ray tube, even with a small gate leakage current, exhibits an induced voltage on the gate electrode by the anode bias voltage, resulting in a very unstable operation and finally a failure. The induced gate voltage is apparently caused by charging at the insulating spacer of the miniature X-ray tube through the gate leakage current of the field emission. The gate leakage current could be a criterion for the successful fabrication of miniature X-ray tubes.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.64.1-64.1
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• 2012

Next generation displays such as high performance LCD, AMOLED, flexible display and transparent display require specific TFT back-planes. For high performance TFT back-planes, low temperature poly silicon (LTPS), and metal-oxide semiconductors are studied. Flexible TFT backplanes require low temperature processible organic semiconductors. Not only development of active semiconducting materials but also design and synthesis of semiconductor corresponding gate dielectric materials are important issues in those display back-planes. In this study, we investigate the high heat resistant polymeric gate dielectric materials for organic TFT and inorganic TFT with good insulating properties and processing chemical resistance. We also controlled and optimized surface energy and morphology of gate dielectric layers for direct printing process with solution processible organic and inorganic semiconductors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.