• 제어로봇시스템학회논문지
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• 제4권3호
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• pp.295-300
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• 1998

In this paper, we point out the possibility of the divergence of control input caused by the estimation error of delay-time when general iterative learning algorithms are applied to a class of linear dynamic systems with time-delay in which delay-time is not exactly measurable, and then propose a new type of iterative learning algorithm in order to solve this problem. To resolve the uncertainty of delay-time, we propose an algorithm using holding mechanism which has been used in digital control system and/or discrete-time control system. The control input is held as constant value during the time interval of which size is that of the delay-time uncertainty. The output of the system tracks a given desired trajectory at discrete points which are spaced auording to the size of uncertainty of delay-time with the robust property for estimation error of delay-time. Several numerical examples are given to illustrate the effeciency of the proposed algorithm.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.481-482
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• 2011

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor values at the mode boundary as functions of the input voltage and the time delay.

• 전기학회논문지
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• 제58권1호
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• pp.193-198
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• 2009

In this paper, we consider the design problem of delay-dependent robust $H{\infty}$ controller of discrete-time descriptor systems with parameter uncertainties and interval time-varying delays in state and control input by delay-dependent LMI (linear matrix inequality) technique. A new delay-dependent bounded real lemma for discrete-time descriptor systems with time-varying delays is derived. The condition for the existence of robust $H{\infty}$ controller and the robust $H{\infty}$ state feedback control law are proposed by LMI approach. A numerical example is demonstrated to show the validity of the design method.

• 한국음향학회지
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• 제32권6호
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• pp.525-531
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• 2013

본 논문은 파워 상호보완 윈도우를 이용한 지연 감소 알고리즘을 IntMDCT(Integer Modified Discreate Cosine Transform)에 적용하고자 제안한다. 기존에 사용하는 변환 방식인 MDCT는 정수 입력에 대해 실수 값을 출력하므로 데이터의 확장을 야기 시킨다. 이에 정수 대 정수 변환인 IntMDCT 기술이 등장했다. 하지만 IntMDCT는 MDCT(Modified Discreate Cosine Transform)처럼 알고리즘 지연을 갖는 문제점을 가지고 있다. 지연은 실시간 통신을 목표로 하는 환경에 있어 중요한 이슈로 자리 잡고 있다. 이러한 샘플의 지연을 최소화하기 위해 제안하는 알고리즘을 적용하고 성능을 평가한 결과, IntMDCT에서 발생하는 샘플 지연이 절반으로 감소하는 것을 확인 할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• ETRI Journal
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• 제22권3호
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• pp.1-9
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• 2000

Self-Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP-SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP-SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP-SCFQ can have the rate proportional property. RP-SCFQ is appropriate for high-speed packet-switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst-case input traffic conditions.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2001년도 춘계학술대회 학술발표 논문집
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• pp.140-143
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• 2001

In this paper, a control problem of the Takagi-Sugeno(TS) fuzzy system with time-varying input delay is considered. It is well known that the delay is one of the major sources responsible for the instability of the controlled system. A systematic design technique is developed based on the Lyapunov-Razumikhin stability theorem. A sufficient condition for the global asymptotic stability of the TS fuzzy systems is formulated in terms of linear matrix inequalities (LMIs). The derived condition can deal with any time-varying input delay within the admissible bound. The effectiveness of the proposed controller design technique is demonstrated by a numerical simulation.

• 제어로봇시스템학회논문지
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• 제4권3호
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• pp.308-314
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• 1998

This paper studies the problem of computing the Hankel singular values and vectors in the input delay systems. It is shown that the Hankel singular values are solutions to a transcendental equation and the Hankel singular vectors are obtained from the kernel of the matrix. The computation is carried out in state space framework. Finally, Hankel approximation of a simple example shows the usefulness of this study.

• 정보처리학회논문지A
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• 제17A권1호
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• pp.27-32
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• 2010

Logical Effort의 기법은 회로의 지연 값을 간단한 필산으로 신속하게 측정할 수 있는 기술이다. 이 기법은 설계 공정 시간을 절약하는 장점도 있지만 고정 지연이라는 설계조건에서 회로의 면적이나 전력의 최소화를 도출할 수 있는 논리 경로를 설계하는데 약점도 있다. 이 논문에서는 균형 지연 모형을 제안하고 이 방법을 기반으로 논리경로에서 전력-지연 효율성을 최적화하는 기법을 제안하고자 한다. 본 논문의 기법을 사용하여 8-input AND 게이트의 3가지 서로 다른 설계 회로를 모의 시험한 결과 기존 Logical Effort의 기법보다 약 40%정도 전력 소비의 효율성이 향상되었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2562-2567
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• 2005

This paper suggests a new method discretization of nonlinear system using Taylor series expansion and zero-order hold assumption. This method is applied into the sampled-data representation of a nonlinear system with input time delay. Additionally, the delayed input is time varying and its amplitude is bounded. The maximum time-delayed input is assumed to be two sampling periods. Them mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. And 'hybrid' discretization scheme that result from a combination of the ‘scaling and squaring' technique with the Taylor method are also proposed, especially under condition of very low sampling rates. The computer simulation proves the proposed algorithm discretized the nonlinear system with the variable time-delayed input accurately.