• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.466-471
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• 2014

An asynchronous optical packet-switching (AOPS) node with load-balancing capability can achieve better performance in reducing the high packet-loss ratio (PLR) and time delay caused by unbalanced traffic. This paper proposes a novel dynamic load-balancing algorithm for an AOPS node with limited buffer and without wavelength converters, and considering the data flow distribution and service levels. By calculating the occupancy state of the output ports, load state of the input ports, and priorities for data flow, the traffic is balanced accordingly. Simulations demonstrate that asynchronous variant data packets and output traffic can be automatically balanced according to service levels and the data flow distribution. A PLR of less than 0.01% can be achieved, as well as an average time delay of less than 0.46 ns.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.853-861
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• 2009

In this paper, we propose the architecture of a multi-band receiver which can receive X-band, Ku-band, K-band and Ka-band signals. For implementing this architecture, we designed a wideband and high power VCO with a buffer stage. In order that a buffer does not affect the characteristic of a oscillation in steady state condition, output impedance of a oscillation part and input impedance of a buffer are orthogonally crossed. The fabricated VCO meets the performance parameter of the multi-band receiver which has a $14.00{\sim}15.20\;GHz$ bandwidth with respect to the tuning voltage, $0.0{\sim}8.0\;V$, and output power of $12{\sim}13\;dBm$.

• Journal of Korean Institute of Industrial Engineers
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• v.30 no.4
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• pp.306-316
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• 2004

We present a closed form approximate analytical model to estimate the expected waiting times for the storage and retrieval requests of an automated storage/retrieval (AS/R) system, assuming that the storage/retrieval (S/R) machine idles either at the rack or at the input/output point. The expected waiting times (and the associated mean queue lengths) can play an important role to decide whether the performance of a stable AS/R system is actually acceptable, to determine buffer size (or length) of the input conveyor, and to compute the number of the rack openings which is required to hold the loads which are requested by processing machines but waiting in the rack to be retrieved by the SIR machine. This model can be effectively used in the early design stage of an AS/R system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Korean Ceramic Society
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• v.42 no.3 s.274
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• pp.178-181
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• 2005

Silicon oxynitride (SiON) layers deposited upon a $SiO_2/Si$ buffer layer placed upon silicon wafers have been obtained by using PECVD from $SiH_4,\;N_2O$, and $N_2$. It can be seen that the refractive index, measured by using a prism coupler, for the SiON films can be varied between 1.4480 and 1.4958 at a wavelength of 1552 nm by changing the process parameters. Optical planar waveguides with a thickness of $6{\mu}m$ and a refractive index contrast ($\Delta$n) of $0.36\% have been deposited. Also, etching experiments were performed using ICP dry etching equipment on thick SiON films grown onto Si substrates covered by a thick $SiO_2$ buffer layer. A polarization maintaining single-mode fiber was used for the input and a microscope objective for the output at $1.55{\mu}m$. As a result, a low index contrast SiON based waveguide is fabricated with easily adjustable refractive index of core layer. It illustrates that the output intensity mode is a waveguiding single-mode.