Browse > Article

Implementation of Channel Coding System using Viterbi Decoder of Pipeline-based Multi-Window  

Seo Young-Ho (유한대학교 전자정보과)
Kim Dong-Wook (광운대학교 전자재료공학과 디지털설계 및 테스트 연구실)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.9, no.3, 2005 , pp. 587-594 More about this Journal
Abstract
In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.
Keywords
Channel Coding; Viterbi Decoder; VLSI; FPGA;
Citations & Related Records
연도 인용수 순위
  • Reference
1 A. K. Yeung and J. Rabaey, 'A 210-Mb/s, radix-4 bit-level pipelined Viterbi decoder,' ISSCC Dig. Tech. Papers, pp. 88 - 89, Feb. 1995
2 H. Dawid, S. Bitterlich, and H. Meyr, 'Trellis pipeline-interleaving: A novel method for efficient Viterbi decoder implementation,' in Proc IEEE Int. Symp. Circuits and Systems, vol. 4, San Diego, CA, May 1992, pp. 1875-1878
3 C. M. Rader, 'Memory management in a Viterbi decoder,' IEEE Trans. Commun., vol. 29, pp. 1399 - 1401, Sept. 1981   DOI
4 J. Sparso, H. N. Jorgensen, E. Paaske, S. Pedersen, and T. Rubner-Petersen, 'An areaefficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures,' IEEE J. Solid-State Circuits, vol. 26, pp. 90 - 96, Feb. 1991   DOI   ScienceOn
5 IEEE Std. 1076-1993, 'VHDL language reference manual', IEEE Press, New Jersey 1994
6 Y. N. Chang, H. Suzuki, and K. K. Parhi, 'A 2-Mb/s 256-State 10-mW Rate-1/3 Veterbi Decoder', IEEE Journal of Solid-State Circuits, Vol. 35, No.6, June. 2000
7 A. J. Viterbi, 'Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,' IEEE Trans. Inform. Theory, vol. IT-13, pp. 260 - 269, Apr. 1967
8 G. D. Forney, Jr., 'The Viterbi algorithm,' Proc. IEEE, Vol. 61, No.3, pp. 268-278, Mar. 1973
9 J. K. Hinderling et al., 'CDMA mobile station modem ASIC,' IEEE J. Solid-State Circuits, vol. 28, pp. 253 - 260, Mar. 1993   DOI   ScienceOn
10 R. Cyper and C. B. Shung, 'Generalized trace-back techniques for survivor memory management in the Viterbi algorithm,' Proc. GLOBECOM, vol. 2, pp. 1318 - 1322, Dec. 1990