• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1246-1264
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• 2000

An input-output buffering switch operates in either of tow different cell loss modes; Backpressure mode and Queueloss mode. In the previous studies, the Backpressrue mode is more effective at low traffic loads, and the Queueloss mode performs better at high traffic. We propose a new operation mode, called Hybrid mode, which adopts the advantages of he Backpressure and the Queueloss mode. Backpressure and Queueloss modes are distinguished from whether a cell loss occurs at the output buffer or not when output buffer overflows, irrespective of input buffer status. In order to simply combine Backpressure and Queueloss mode, the change of input traffic load must be measured. However, in the Hybrid mode, simply both of the input and output buffer overflow and checked out to determine the cell discard. The performance of the Hybrid mode is compared with those of the Backpressure and the Queueloss mode under random and bursty traffic. This paper show that the Hybrid mode always gives the best performance results for most ranges of load values.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.123-133
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• 1994

This paper presents an output arbitrator for input buffering ATM (Asynchronous Transfer Mode) switches using neural networks. To avoid blocking in ATM switches with blocking characteristics, it is required to buffer ATM cells in input buffer and to schedule them. The N$\times$N request matrix is divided into N/16 submatrices in order to get rid of internal blocking systematically in scheduling phase. The submatrices are grouped into N/4 groups, and the cells in each group are switched alternatively. As the window size of input buffer is increases, the number of input cells switched in a time slot approaches to N. The selection of nonblocking cells to be switched is done by neural network modules. N/4 neural network modules are operated simultaneously. Fast selection can be achieved by massive parallelism of neural networks. The neural networks have 4N neurons and 14N connection. The proposed method is implemented in C language, and the simulation result confirms the feasibility of this method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.