• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.543-546
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• 2006

최근 여러 연구에서 다양한 종류의 멀티 모드 하이브리드 동력 전달계가 제안되고 있다. 멀티모드 동력전달계는 두 개 이상의 다른 유성기어식 하이브리드 시스템으로 이루어져 있으며 클러치를 사용하여 각 상황에 유리한 유성기어 시스템을 사용하여 주행한다. 각 유성기어 시스템의 단점들을 보완할 수 있기 때문에 단일 모드를 사용하여 주행했을 때보다 여러 면에서 높은 성능을 보인다. 일반적으로 유성기어식 하이브리드 시스템은 크게 입력, 출력, 복합 분기식의 세 가지 종류로 나눌 수 있는데 이 논문에서는 입력 및 복합 분기식 구조의 특징을 분석해 보았다. 또한 시뮬레이션을 통해 입력, 복합 분기식 구조를 사용하여 듀얼 모드를 구성하였을 때 단일 모드와 비교하여 어느정도의 성능을 보이는지 알아보았다.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of the Korean Society of Hazard Mitigation
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• v.10 no.6
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• pp.35-43
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• 2010

This study was carried out to find reliable relations between various concrete strength properties which are used as input data in concrete pavement design program. Concretes were made from different sources of coarse grained(granite, limestone and sandstone) and fine grained aggregates such as natural sand, washed sand and crushed sand. From strength test results, model equations were obtained based on the relation between strengths. For each coarse grained aggregate, models for compression-flexural strengths, compression-split tensile strengths, compressive strength-modulus and flexural-split tensile strengths with age were obtained. For concrete mixed with gneiss granite aggregates, concrete strengths were obtained from numerical mean values of concrete strengths mixed with fine grained aggregates. In addition models for concrete split tensile strengths and modulus values were provide by averaging numerically the estimated values obtained from the derived relationship and the experimental values. This is due to more scattered values of split tensile strengths and modulus values than other strength properties. Finally criteria for drying shrinkage strain as well as Poisson's ratio for concrete used in pavement were presented for all mixes with differed coarse grained aggregates.

• The Journal of the Acoustical Society of Korea
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• v.27 no.6
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• pp.309-318
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• 2008

In this paper, we discuss a method for efficiently coding the high-band signal in the split-band coding approach where an input signal is divided into two bands and then each band may be encoded separately. Generally, and especially through the research on the artificial bandwidth extension (BWE), it is well known that there is a correlation between the two bands to some degree. Therefore, some coding gain could be achieved by utilizing the correlation. In the BWE-prediction-based coding approach, using a simple linear BWE function may not yield optimal results because the correlation has a non-linear characteristic. In this paper, we investigate the new coding scheme more in details. A few representative BWE functions including linear and non-linear ones are investigated and compared to find a suitable one for the coding purpose. In addition, it is also discussed whether there are some additional gains in combining the BWE coder with the predictive vector quantizer which exploits the temporal correlation.

• Journal of Power Electronics
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• v.15 no.2
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• pp.389-398
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• 2015

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

• Proceedings of the KWS Conference
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• 2003.05a
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• pp.99-101
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• 2003

This study deals with the resistance spot welding of aluminized steels. According to the test results it was clear that the weldability of aluminized steels was equivalent to or better than that of Zn coated steel. Microstructural inspection revealed that molten aluminum that was repelled from the weld during the process, piled up at the split zone. The test results also demonstrated that the weld metal of aluminized steels could hardly produce the weld crack even higher welding heat Input was applied.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• Proceedings of the KOSOMBE Conference
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• v.1989 no.05
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• pp.19-22
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• 1989

This paper represents a syntactic peak detection algorithm which detects peaks in the ECG signal. In the algorithm, the input waveform is linearly approximated by "split-and-merge" method, and then each line segment is symbolized with primitive set. The peeks in the symbolized input waveform are recognized by the finite-state automata, which the deterministic finite-state language is parsed by. This proposed algorithm correctly detects peaks in a normal ECG signal as well as in the abnormal ECG signal such as tachycardia and the contaminated signal with noise.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2207-2214
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• 2010

Underwater acoustic(UWA) communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of UWA channel causes signal distortion and error floor. In this paper, we proposed split input bits of channel decoder using method of maximum value, average value, LLR value for optimal estimation. Channel coding method is LDPC(N size=16000) standard in DVB-S2. As shown in simulation results, the performance of LLR value method is better than other methods.