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http://dx.doi.org/10.5573/ieie.2017.54.2.047

Design of a 10-bit SAR ADC with Enhancement of Linearity On C-DAC Array  

Kim, Jeong Heum (Department of Electronic Engineering, Inha University)
Lee, Sang Heon (Department of Electronic Engineering, Inha University)
Yoon, Kwang Sub (Department of Electronic Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.54, no.2, 2017 , pp. 47-52 More about this Journal
Abstract
In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).
Keywords
SAR ADC; Linearity; C-DAC; ADC; bio-signal;
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Times Cited By KSCI : 2  (Citation Analysis)
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