• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.569-570
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• 2008

This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Journal of Arbitration Studies
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• v.21 no.2
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• pp.85-112
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• 2011

These days utilization of copyright in daily life and economic activities is becoming more important than ever, and IT technology is developing day by day. Along with those fact, copyright infringement and dispute is naturally increasing. This thesis dealt with the 3 different issues of ADR on copyright. The First part, introduce ADR system that was performed by Korea Copyright Committee according to Copyright law. This paper evaluate the committee's efforts to provide resolution of copyright disputes via conciliation was effective. So it needs to be look over several countries' ADR, beside conventional judicial remedy. And Korea's copyright conciliation system which is successfully operating also introduced. Second, In many countries, including South Korea are take advantage of conciliation as the way to settle down the dispute over copyright. Furthermore, looked over if we can use arbitration as tool to settle dispute or not. Currently in Korea, patent dispute is handled by Industrial Property Dispute Conciliation Committee(The Invention Promotion Act Ch.5) and Layout-design Review and Mediation Committee(The Act on the Layout-designs of Semiconductor Integrated Circuits Art.29-34), but using performance of those two committee is still too low. In comparison, the copyright committee, a affiliation organization of the ministry of culture, sports and tourism has much more result in conciliation compare with patent dispute. Copyright disputes has arbitrability of it's subject-matter and many regulating organs are interested in it. (especially, binding of arbitral award and final resolution). Take advantage of both conciliation and arbitration could be good way to resolve copyright disputes. Third, the writer look at the proposal on the creation of Northeast Regional Center for Intellectual Property ADR. Because of the nature of copyright and rapid development of internet technology, international use of work become more frequent and accordingly infringement cases are increasing. The role of commercial arbitration regimes and institutions which has progressed significantly worldwide level, but which has only just begun in the intellectual property ADR area, leads also to a clash of often very different legal cultures and protection in a market economy. International cooperation in regional area with conflict interests becomes an important alternative. But it will depend on the building of regional institutions and mechanisms. The feasibility of this proposal and preconditions were examined. Establishment of new international organization requires a lot of time, cost and efforts. And risk of failure is much too high. Therefore factual, statistical review should be preceded. In addition, technical measures, such as on-line arbitration is necessary to review also. Furthermore in order to establish new organization, the relative law, legal environment, public sentiment and international compliance must be carefully considered with factual review about the needs and economic benefits of each country Yet on complex regulatory matters such as IP and ADR, a great deal of the potential benefits from international standards arises not from the international legal framework nor even the formal content of national legislation, but from the informed and effective use made of the possibilities within the system, including by policymakers and regulators.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.26-32
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• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.663-665
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• 2004

Ethernet-based passive optical network(EPON) technology is being considered as a promising solution for next-generation broadband access network. It must have the property of high efficiency, low cost, and support quality of service(QoS). A major feature for this new architecture is the use of a shared transmission media between all connected optical network unit(ONU). Hence, medium access control(MAC) arbitration mechanisms are essential for the successful implementation of EPON. In this paper we propose a simple dynamic bandwidth allocation(DBA) algorithm that improves the performance of network and supports IP-based multimedia applications with the bursty data traffic. In addition, we introduce analytic models of proposed algorithms and prove the system based on our algorithm to be asymptotically stable. Simulation results show the new DBA algorithm provides high bandwidth efficiency and low queueing delay of ONU in EPON.

• Journal of KIISE:Information Networking
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• v.31 no.1
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• pp.11-19
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• 2004

P2P network environments provide users with direct data transmission and sharing facilities and those environments can be classified into hybrid P2P network environments and pure P2P network environments according to the arbitration mechanism among the peers in the network. In hybrid P2P network environments, there exists a server that maintains index information for the data to be shared and network isolation does not occur because every peer always keeps connection to the server. In pure P2P network environments, however, each peer directly connects to another peer and gets services without server intervention, and so, network isolation can occur when the mediating peer fails to work. In this paper. we propose a scheme for each peer to keep connection to other peers continuously by maintaining IP addresses of its neighbor peers and connecting to the peers when the mediating peer fails to work. Although the P2P application that uses our proposed framework should obtain one or more IP addresses of the neighbor peers manually, after instantiation, the application can do its job while maintaining connection to the network continuously and automatically. To evaluate our proposed scheme, we measured and analyzed the time for a peer to reconnect to the network when the mediating peer fails and the network isolation occurs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.