• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12A
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• pp.1912-1923
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• 2000

본 논문에서는 내장된 자체 테스트(BIST: Built-In Self Test) 기법의 구현에 관해 기술한다. 내장된 자체 테스트 기법이 적용된 칩은 영상 처리 및 3차원 그래픽스용 부동 소수점 DSP 코어인 FLOVA이다. 내장된 로직 자체 테스트 기법은 FLOVA의 부동 소수점 연산 데이터 패스에 적용하였으며, 내장된 메모리 자체 테스트 기법은 FLOVA에 내장된 데이터 메모리와 프로그램 메모리에 적용하였다. 그리고, 기판 수준의 테스팅을 지원하기 위한 표준안인 경계 주사 기법(IEEE 1149.1)을 구현하였다. 특히, 내장된 자체 테스트 로직을 제어할 수 있도록 경계주사 기법을 확장하여 적용하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1611-1614
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• 2002

하나의 보드에 대한 소자들의 테스팅을 위해서 IEEE 1149.1이 제안되었고 완전한 테스팅을 지원한다. 하지만 여러 보드에 대해서는 불가능하여 IEEE 1149.1을 확장한 시스템 레벨의 테스팅 방법이 제안되었다. 기존의 IEEE 1149.1을 확장한 방법은 보드 레벨의 테스팅과 시스템 레벨의 테스팅이 하나의 데이터 패스에 의해서 테스트 시간이 길고 비효율적이다. 본 논문에서는 보드 레벨 테스팅과 시스템 레벨 테스팅을 구분하여 불필요한 테스트 데이터 이동을 줄여 테스트 시간을 줄이고 효율적인 방법을 제시한다. 그리고 이를 지원하기 위한 Path Select Unit을 설계한다. 구현된 PSU는 작은 게이트 사이즈로 적은 테스트 비용으로도 효율적으로 시스템 레벨 테스팅이 가능해진다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.209-216
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• 2001

A key advantage of boundary scan technology is the ability to observe data at device inputs and control data at device outputs, independent of on-chip system logic. But, this method has a disadvantage for detecting of faults that changes their states very fast. We present a method to solve this problem and make it possible to detect the signals. We shown the simulation results of testing a circuit that has fast signal above the clock speed.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1635-1638
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• 2002

IEEE Std.1149.1 표준의 제정으로 경계주사는 규격화되었다. 그러나 이러한 표준의 제정에도 불구하고 실제 보드 테스트를 수행하는 데에는 아직도 많은 어려움을 가지고 있다. 본 연구에서는 IEEE Std.1149.1의 표준을 만족하면서도 기존의 방법보다 안전성에서 우위를 보임과 동시에 보다 높은 고장 검출률을 가지는 경계주사 테스트 시스템의 새로운 구현 기법을 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.226-232
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• 2005

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.54-64
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• 2002

Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.