• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Korean Society of Industry Convergence
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• v.23 no.6_2
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• pp.1051-1058
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• 2020

The chemical mechanical planarization (CMP) is a process of physically and chemically polishing the semiconductor substrate. The planarization quality of a substrate can be evaluated by the within wafer non-uniformity (WIWNU). In order to improve WIWNU, it is important to manage the pad profile. In this study, a device capable of non-contact measurement of the pad thickness profile was developed. From the measured pad profile, the profile of the pad surface and the groove was extracted using the envelope function, and the pad thickness profile was derived using the difference between each profile. Thickness profiles of various CMP pads were measured using the developed PMS and envelope function. In the case of IC series pads, regardless of the pad wear amount, the envelopes closely follow the pad surface and grooves, making it easy to calculate the pad thickness profile. In the case of the H80 series pad, the pad thickness profile was easy to derive because the pad with a small wear amount did not reveal deep pores on the pad surface. However, the pad with a large wear amount make errors in the lower envelope profile, because there are pores deeper than the grooves. By removing these deep pores through filtering, the pad flatness could be clearly confirmed. Through the developed PMS and the pad thickness profile calculation method using the envelope function, the pad life, the amount of wear and the pad flatness can be easily derived and used for various pad analysis.

• Infection and chemotherapy
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• v.50 no.4
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• pp.319-327
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• 2018

Background: Lancet-related needlestick injuries (NSIs) occur steadily in clinical practices. Safety-engineered devices (SEDs) can systematically reduce NSIs. However, the use of SEDs is not active and no study to guide the implementation of SEDs was known in South Korea. The lancet-related NSIs may be eliminated to zero incidence using a SED lancet with effective sharp injury protection and reuse prevention features. Materials and Methods: We implemented a SED lancet by replacing a conventional prick lancet in a tertiary hospital in a sequential approach. A spot test of the new SED was conducted for 1 month to check the acceptability in practice and a questionnaire survey was obtained from the healthcare workers (HCWs). A pilot implementation of the SED lancet in 2 wards was made for 1 year. Based on these preliminary interventions, a hospital-wide full implementation of the SED lancet was launched. The incidence of NSIs and cost expenditure before and after the intervention were compared. Results: There were 29 cases of conventional prick lancet-related NSIs for 3 years before the full implementation of SED lancet. The proportion of prick lancet-related NSIs among yearly all kinds of NSIs during two years before the pilot study was average 11.7% (22/188). Pre-interventional baseline incidence of all kinds of NSIs was 7.01 per 100 HCW-years. After the full implementation of SED lancet, the lancet-related NSIs became zero in the 2nd year (P = 0.001). The average direct cost of 18,393 US dollars (USD) per year from device and post-exposure medical care before the intervention rose to 20,701 USD in the 2nd year of the intervention. The incremental cost-effectiveness ratio was 210 USD per injury avoided. Conclusion: The implementation of a SED lancet could eliminate the lancet-related NSIs to zero incidence. The cost increase incurred by the use of SED lancet was tolerable.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.382-390
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• 2017

In this paper, we consider particular exposure scenarios to evaluate human effects for inductive commercial wireless charging device operating at low frequency. The coil used in this study is the A10 model in Qi standard proposed by WPC(Wireless Power Consortium), and input power is 5 W to the operating frequency of 155 kHz. In perfectly aligned condition, the max leakage magnetic field is $257.58{\mu}T$ which is obtained at the side of the device, and it is exceeded about 7.4 times of the ICNIRP 1998 reference level. The SAR is evaluated with homogeneous phantom which has electric constants of wet skin. The max value of the SAR is $134.47{\mu}W/kg$ which is obtained at the side of the device also, and it is much lower than the international guidelines. Especially, it showed higher SAR values in case of misalignment condition, so we will need to consider the misalignment condition importantly when we evaluate human effects for wireless power transfer system.

• Journal of Life Science
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• v.18 no.9
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• pp.1257-1262
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• 2008

Photodynamic therapy (PDT) is a treatment utilizing the generation of singlet oxygen and other reactive oxygen species (ROS), which selectively accumulated in target cells. Genistein, soy-derived phytoestrogen, is one of the anticancer agents found in soybean. In the current study, we investigated the effect of photofrin-induced PDT and genistein on apoptotic cell death in head and neck cell line (AMC-HN3) to confirm the photodynamic therapy of genistein. It was determined by MTT assay that the combination group had more cytotoxicity effect than PDT group alone. Combination of photofrin PDT and genistein induced apoptosis more when comparing with PDT alone. Our data also showed that ROS was increased in combination therapy, indicating apoptosis by mitochondrial damage. These results indicated that the combination of photofrin PDT and genistein showed more cytotoxic effect and induced apoptosis in head and neck cancer cell line.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.8
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• pp.120-128
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• 2004

The impulse between launch vehicle and atmosphere can generate a lot of noise and vibration during the process of launching a satellite. Structurally, the electronic equipment of a satellite consists of an aluminum case containing PCB. Each PCB has resistors and IC. Noise and vibration of the wide frequency band are transferred to the inside of fairing, subsequently creating vibration of the electronic equipment of the satellite. In this situation, random vibration can cause malfunctioning of the electronic equipment of the device. Furthermore, when the frequency of random vibration meets with natural frequency of PCB, fatigue fracture may occur in the part of solder joint. The launching environment, thus, needs to be carefully considered when designing the electronic equipment of a satellite. In general, the safety of the electronic equipment is supposed to be related to the natural frequency, shapes of mode and dynamic deflection of PCB in the electronic equipment. Structural vibration analysis of PCB and its electronic components can be performed using either FEM or vibration test. In this study, the natural frequency and dynamic deflection of PCB are measured by FEM, and the safety of the electronic components of PCB is evaluated according to the results. This study presents a unique method for finite element modeling and analysis of PCB and its electronic components. The results of FEA are verified by vibration test. The method proposed herein may be applicable to various designs ranging from the electronic equipments of a satellite to home electronics.

• Journal of Sensor Science and Technology
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• v.27 no.5
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• pp.300-305
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• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1304-1314
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• 1988

An experimental study of the influences of HF concentration, current density, reaction time and the silicon surface, on the formation and properties of porous silicon are reported. The SOI (Silicon-On-Insulator) strip lines with 100 um width are fabricated at room temperature by anodic oxidation of PSL (Porous Silicon Layers). The stress on the silicon island induced by the anodic oxidation can be avoided by the two-step PSL formation technique. At the final step of IC fabrication process, device isolation will be achieved at room temperature by this method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.