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http://dx.doi.org/10.6117/kmeps.2012.19.4.071

3D Integration using Bumpless Wafer-on-Wafer (WOW) Technology  

Kim, Young Suk (The University of Tokyo, School of Engineering, DISCO CORPORATION)
Publication Information
Journal of the Microelectronics and Packaging Society / v.19, no.4, 2012 , pp. 71-78 More about this Journal
Abstract
This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.
Keywords
3D-IC; TSV; Bumpless; WOW; CMOS transistor;
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