• Proceedings of the Korean Information Science Society Conference
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• 2001.10b
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• pp.361-363
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• 2001

반도체 패키지의 마킹검사(marking inspection)를 위해서는 입력 영상으로부터 검사할 패키지의 정확만 위치 검출과 패키지 윗면에 나타난 제작사 로고, 문자, Pin1 딤플의 추출이 필수적이다. 본 연구는 마킹검사를 위한 선행 연구로 마킹검사를 수행할 때, 검사할 IC 패키지의 위치와 방향을 정확하게 검출하는 것을 목적으로 하고 있다. IC 패키지의 외곽을 구성하는 리드의 명도 값은 트레이의 명도 값과 큰 차이를 나타낸다. 그러나 IC 패키지의 방향을 나타내는 Pin1 딤플은 배경과 동일한 색상으로 다만 약간 오목하게 들어가서 명도 값의 차이가 미세하다. 이러한 두 가지 상이한 특징을 효과적으로 처리하기 위하여 적응적 다중 이진화 방법을 제시하였다. 76개의 명도 영상에 대한 실험 결과 제안된 이진화 방법은 매우 효과적이었으며, 이진화된 영상으로부터 IC 패키지의 정확한 위치 검출과 방향 확인이 가능하였다.

• Electronics and Telecommunications Trends
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• v.4 no.4
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• pp.17-33
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• 1989

Hermetic 패키지는 재질 특성상 Plastic 패키지보다 환경내구성이 우수하고 수명이 긴 장점이 있으나, 가격이 높고 사용자의 주문에 의한 수작업으로 수급이 어려운 단점이 있다. 한편 Plastic 패키지는 가격이 낮고 수급이 용이한 반면 환경 특히 습기로 인한 고장으로 Hermetic 패키지보다 신뢰도가 낮아서 고신뢰도를 요구하는 군사용 및 산업용기기에서의 사용은 기피되어 왔다. 그러나 최근 Plastic 패키지의 단점을 개선하려는 노력으로 반도체칩의 수율 향상과 더불어 습기에 강한 재료가 개발되고 웨이퍼 제조기술이 발전됨에 따라 Plastic 패키지의 신뢰도가 향상되어 통신기기등 산업용 기기에까지 사용영역을 확대해 가고 있다. 또한 국내의 통신시장 개방에 따라 통신시스팀의 성능개선 및 신뢰성 제고를 통한 대외 경쟁력이 요구되어 통신시스팀에 Plastic 패키지 사용에 대한 인식이 증대하는 추세이다. 본고에서는 IC 패키지(Hermetic, Plastic)의 특성 및 성능을 비교 분석하고 이와 병행하여 Plastic 패키지의 최근 기술동향을 파악함으로써 통신시스팀에 사용하는 IC 패키지에 대한 고려사항을 제시하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.25 no.1
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• pp.46-51
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• 2024

Drone was first used for military purposes but as the range of use has recently expanded. It is being widely used in various industrial fields such as agriculture, service, logistics, and leisure. Lithium polymer batteries are lightweight and highly efficient, so they are mainly used as power supplies for drones. Accordingly, the need for lightweight and high energy density lithium polymer batteries has increased in order to supply stable power to drone. However, lithium polymer batteries can lead to ignition and explosion due to overcharging, short circuit, etc., so they must be used with a protective circuit installed. The protection circuit consists of a protection IC that monitors the voltage of the lithium polymer battery and a dual N-channel MOSFET that acts as a switch in case of overcharge and overdischarge. Therefore, this paper was implemented in one package form using a battery protection IC and a MOSFET semiconductor die chip serving as a switch. When implemented as a one chip package IC, at least 67% of savings compared to existing parts can be achieved.

• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.160-162
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• 2002

본 논문은 LCD구동 IC 패키지 제조 분야에서 사용되는 TAB IC블랭킹 금형에 대해 신속하고 합리적인 설계를 수행하기 위하여 금형설계와 관련된 다년간 축적된 경험적지식과 설계지식을 전산정보화하여 지식베이스를 구축하였고, 설계에 필요한 TAP IC 패키지의 형상정보를 제공받기 위하여 표준적인 특징형상 입력모듈을 제안하였다. 또한 지식베이스를 통해 산출된 설계 결과를 3차원 모델러와 연계하여 3차원 형상생성 및 가공도면의 자동화를 실현하여, 기존의 TAB If 블랭킹 금형설계자 뿐만 아니라 신입설계자도 바로 실무에 적용할 수 있는 시스템으로 발전시키고자 한다.

• The KIPS Transactions:PartB
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• v.9B no.2
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• pp.245-254
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• 2002

IC package marking inspection system using machine vision locates and identifies the target elements from input image, and decides the quality of marking by comparing the extracted target elements with the standard patterns. This paper proposes an adaptive multi-level thresholding (AMLT) method which is suitable for a series of operations such as locating the target IC package, extracting the characters, and detecting the Pinl dimple. It also proposes a dynamic matching unit selection (DMUS) method which is robust to noises as well as effective to catch out the local marking errors. The main idea of the AMLT method is to restrict the inputs of Otsu's thresholding algorithm within a specified area and a partial range of gray values. Doing so, it can adapt to the specific domain. The DMUS method dynamically selects the matching unit according to the result of character extraction and layout analysis. Therefore, in spite of the various erroneous situation occurred in the process of character extraction and layout analysis, it can select minimal matching unit in any environment. In an experiment with 280 IC package images of eight types, the correct extracting rate of IC package and Pinl dimple was 100% and the correct decision rate of marking quality was 98.8%. This result shows that the proposed methods are effective to IC package marking inspection.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.43-50
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• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.3
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• pp.15-22
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• 2008

Applications of bonded dissimilar materials such as integrated circuit(IC) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in bonded joints of dissimilar materials. In order to investigate the IC package crack propagating from the edge of die pad and resin, the fracture parameters of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method(BEM). From these results, crack propagation direction and path by thermal stress in the IC package were numerically simulated with boundary element method.

• Journal of Welding and Joining
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• v.27 no.3
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• pp.4-9
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• 2009