• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.114-126
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• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3175-3184
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• 1997

To support large storage capacity and real-time characteristics of continuous media storage systems, we need to improve the performance of disk I/O subsystems. To improve the performance, we exploited buffer sharing scheme that reduces the number of disk I/Os. We utilized the advance knowledge of continuous media streams that is used to anticipate data demands, and so Promoting the sharing of blocks in buffers. In this paper, we proposed a buffer replacement algorithm that enables subsequent users requesting the same data to share buffer efficiently. The proposed algorithm manages buffers by utilizing reference interval information of blocks. In order to verify validity of the proposed algorithm, we accomplished simulation experiments and showed the results of performance improvements compared to traditional buffer replacement algorithms.

• The Journal of the Acoustical Society of Korea
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• v.8 no.5
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• pp.95-101
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• 1989

For developing new algorithms or dedicated hardware by using general purpose Digital Signal Processor chip, emulator H/W and simulator S/W are indispensible. But the most of DSP emulators have limitations on H/W flexibility according to their generalized architectures. In this paper, a DSP evaluation system for real time signal processing was developed using TMS 32020. The I/O buffers storing acquisition data of the system were designed to have variable length $(1\sim2048samp1es) &$ sampling frequency $l00\sim8KHz$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.259-262
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• 2013

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.75-80
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• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1059-1067
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• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• Journal of Broadcast Engineering
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• v.25 no.5
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• pp.655-664
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• 2020

Free viewpoint image synthesis technology is one of the important technologies in the MPEG-I (Immersive) standard. RVS (Reference View Synthesizer) developed by MPEG-I and in use in MPEG group is a DIBR (Depth Information-Based Rendering) program that generates an image at a virtual (intermediate) viewpoint from multiple viewpoints' inputs. RVS uses the mesh surface method based on computer graphics, and outperforms the pixel-based ones by 2.5dB or more compared to the previous pixel method. Even though its OpenGL version provides 10 times speed up over the non OpenGL based one, it still shows a non-real-time processing speed, i.e., 0.75 fps on the two 2k resolution input images. In this paper, we analyze the internal of RVS implementation and modify its structure, achieving 34 times speed up, therefore, real-time performance (22-26 fps), through the 3 key improvements: 1) the reuse of OpenGL buffers and texture objects 2) the parallelization of file I/O and OpenGL execution 3) the parallelization of GPU shader program and buffer transfer.