• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• 한국군사과학기술학회지
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• 제5권2호
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• 정보과학회 논문지
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• 제43권11호
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• pp.1216-1222
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• 2016

대규모 웹 서비스의 등장으로 데이터의 규모가 점차 증가하는 추세이다. 이러한 대규모 데이터를 효율적으로 관리하기 위해 MySQL과 MariaDB와 같은 DBMS가 주로 사용되고 있으며, 이들은 데이터 관리를 위한 스토리지 엔진으로 InnoDB를 주로 사용한다. InnoDB는 ACID를 보장할 뿐만 아니라 대규모 데이터 처리에 적합하다는 장점이 있기 때문이다. InnoDB의 경우, I/O 성능 향상을 위해 버퍼 풀을 통해 데이터와 인덱스를 캐싱하며 락 경쟁(lock contention)을 줄이기 위해 다중 버퍼 풀을 지원한다. 그러나 다중 버퍼 풀 기법은 데이터 일관성 오버헤드를 증가시킨다. 본 논문에서는 다중 버퍼 풀 기법의 오버헤드를 분석한다. 실험 결과, 다중 버퍼 풀 기법을 사용함에 따라 락 경쟁이 최대 46.3%까지 완화되었지만 디스크 I/O와 fsync 명령이 증가하면서 DBMS의 처리량이 50.6%까지 떨어지는 현상을 확인하였다.

• 한국진공학회지
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• 제20권1호
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• pp.50-56
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• 2011

본 논문에서는 버퍼막 두께 및 열처리 온도에 따른 ZnO/b-ZnO/p-Si(111) 기반 이종접합 다이오드 전류 특성에 대한 연구가 진행되었고, b-ZnO (ZnO buffer layer) 버퍼막 두께 및 열처리 온도에 따른 p-Si(111) 기판 위에 증착시킨 ZnO 박막의 구조적, 전기적 특성 또한 연구되었다. X-ray diffraction (XRD) 방법을 이용하여 ZnO 박막의 구조적 특성을 측정하였고, semiconductor parameter analyzer를 이용하여 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 I-V 특성을 평가하였다. XRD 분석 결과 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 70 nm에서 ZnO 박막은 우세한 (002) 방향의 c-축 배향성을 갖는 육방정계(hexagonal wurtize) 결정 구조를 나타내었다. 전기적 특성인 운반자 농도, 비저항 값의 경우에는 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 50 nm에서 우수한 전기적 특성(비저항: $2.58{\times}10^{-4}[{\Omega}-cm]$, 운반자 농도: $1.16{\times}10^{20}[cm^{-3}]$)을 보였다. 또한 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 전류 특성은 버퍼막 열처리 온도 $700^{\circ}C$에서 버퍼막 두께가 증가할수록 전류 특성이 향상되는 경향을 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• 한국산학기술학회논문지
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• 제20권7호
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• pp.45-51
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• 2019

현대 파일 시스템은 예기치 못한 시스템 크래시 또는 재난 상황에서도 데이터의 일관성 유지를 위해 저널링 메커니즘을 유지한다. 그러나 저널링은 I/O 처리율을 떨어뜨리는 문제가 있다. 이 성능 저하 문제는 데이터 버퍼와 메타데이터 버퍼간의 오더링 메커니즘과 2단계 버퍼쓰기에서 기인하는데. 특히, 만약 데이터 버퍼와 메타데이터 버퍼가 동시에 저널링이 되면, 2단계 쓰기 때문에 심각한 성능저하가 발생하며, 이는 I/O 성능과 시스템 신뢰도 간의 Trade-off 관계가 있음을 나타낸다. 본 논문은 RFJ라는 신뢰성 있는 고속 저널링 기법을 제안한다. 이 기법은 Ordering enforced writeback 저널링 모드와 selective journaling 메커니즘을 도입해서 높은 신뢰도와 동시에 고성능 I/O가 가능하게 한다. 본 논문에서 제안한 기법의 실험 결과 기존 Ext3 저널링 모드 대비 약 5배 이상 빠른 I/O 처리량을 지원하면서 동시에 Ext3 저널링과 동일한 수준의 신뢰성을 나타는 것을 확인 할 수 있었다.

• 한국재료학회지
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• 제21권1호
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• pp.34-38
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• 2011

In this study, the effects of an annealed buffer layer with different thickness on heterojunction diodes based on the ZnO/ZnO/p-Si(111) systems were reported. The effects of an annealed buffer layer with different thickness on the structural, optical, and electrical properties of zinc oxide (ZnO) films on p-Si(111) were also studied. Before zinc oxide (ZnO) deposition, different thicknesses of ZnO buffer layer, 10 nm, 30 nm, 50 nm and 70 nm, were grown on p-Si(111) substrates using a radio-frequency sputtering system; samples were subsequently annealed at $700^{\circ}C$ for 10 minutes in $N_2$ in a horizontal thermal furnace. Zinc oxide (ZnO) films with a width of 280nm were also deposited using a radio-frequency sputtering system on the annealed ZnO/p-Si (111) substrates at room temperature; samples were subsequently annealed at $700^{\circ}C$ for 30 minutes in $N_2$. In this experiment, the structural and optical properties of ZnO thin films were studied by XRD (X-ray diffraction), and room temperature PL (photoluminescence) measurements, respectively. Current-voltage (I-V) characteristics were measured with a semiconductor parameter analyzer. The thermal tensile stress was found to decrease with increasing buffer layer thickness. Among the ZnO/ZnO/p-Si(111) diodes fabricated in this study, the sample that was formed with the condition of a 50 nm thick ZnO buffer layer showed a strong c-axis preferred orientation and I-V characteristics suitable for a heterojunction diode.

• Mass Spectrometry Letters
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• 제6권4호
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• pp.112-115
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• 2015

In this article, we examine the influences of Ne and He buffer gases under confined Ar⁺ ion cloud in a homemade Paul ion trap in various pressures and confinement times. The trap is of small size (r₀ = 1 cm) operating in a radio frequency (rf) voltage only mode, and has limited accuracy of 13 V. The electron impact and ionization process take place inside the trap and a Faraday cup has been used for the detection. Although the experimental results show that the Ar⁺ ion FWHM with Ne buffer gas is wider than the He buffer gas at the same pressure (1×10^-1 mbar) and confinement time is about 1000 μs, nevertheless, a faster cooling was found with He buffer gas with 500 μs. ultimetly, the obtanied results performed an average cloud tempertures reduced from 1777 K to 448.3 K for Ne (1000 μs) and from 1787.9 K to 469.4 K for He (500 μs)

• ETRI Journal
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• 제25권5호
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• pp.297-304
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• 2003

A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1277-1279
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• 1994

In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.