• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.187-191
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• 2007

In this paper, the catalyst layer is deposited on silicon substrate using magnetron sputtering system and carbon nanotubes(CNTs) were grown in $NH_3\;and\; C_2H_2$ gas by hot-filament plasma enhanced chemical vapor deposition (HFPECVD) system. A growth temperature of carbon nanotubes was changed from $350^{\circ}C\;to\;650^{\circ}C\;by\;100^{\circ}C$. We observed the shape of CNTs by a field-emission scanning electron microscope(FE-SEM) measurement and analyzed the surface characteristic of CNTs layer by contact angle measurement. That is, the growth temperature of CNTs is the important factor leads to the variation of the properties.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.189-194
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• 2018

Nowadays most integrated circuits are built using the bulk CMOS technology, but it has much difficulty in further reduction of the power consumption and die size. As a super low-power technology to solve such problems, the SOI technology attracts great attention recently. In this paper, the study results of the temperature dependency of the hot carrier effects in the n-channel MOSFETs fabricated on the thin SOI substrate were discussed. In spite that the devices employed the LDD structure, the hot carrier effects were more serious than expected due to the high series resistance between the channel region and the substrate contact to the ground, and were found to be less serious for the higher temperature with the more phonon scattering in the channel region, which resulted in reducing the hot electron generation.

• Journal of the Korean Society for Heat Treatment
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• v.14 no.2
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• pp.96-102
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• 2001

$Al_2O_3$-copper alloy has been successfully made by gas atomization, mechanical alloying and hot pressing. In order to investigate microstructure and phase, it has been studied by using scanning electron microscope, transmission electron microscope and X-ray diffractometor. Mechanical properties have been examined using hardness tester and compressive tester according to annealing temperature. Although comparatively large Cu-Al powders are milled, the reaction between Cu-Al and $Cu_2O$ occurs and very fine $Al_2O_3$ particles in the matrix particles (5-10nm) are obtained. Compressive strength of this alloy is more than that of GlidCop Al60.

• Laser Solutions
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• v.4 no.1
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• pp.39-48
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• 2001

This study was performed to evaluate basic characteristics of electron beam weldability for high strength aluminum alloys. The aluminum alloys used were A5083 and A6N01, and A7N01. The principal welding process parameters, such as accelerating voltage, beam current, welding speed and chamber pressure were investigated. The dimension and microstructure of welds were evaluated with OLM, and SEM (EDAX). In addition, weldability variation(cracking) due to process parameters was also evaluated. The degree of cracking in the EB fusion zone appears to be affected mainly by aspect ratio, such that as aspect ratio increases the cracking tendency also increases. The alloying element itself may also affect the hot cracking resistance, but its role is considered to be indirect effect such that the relatively higher vaporization pressure elements of Zn and Mg give deeper weld penetration and thus results in greater cracking tendency.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.3
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• pp.6-11
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• 1977

The noise behavior of the Schottky Barrier Gate FET has been investigated by the use of noise equivalent circuit. It has been found that an additional noise source has to be taken into account in the GaAs SBGFET's biased in the pinch-off region; the intervalley scattering noise and the hot electron noise. In this paper, a noise equivalent circuit has been used to determine the noise parameter which was taken into account influence of the saturation velocity of carrier and parasitic resistance.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.