• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.169-172
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• 2002

The voltage holding ratio(VHR) and the residual DC property in the in-plane switching (IPS) cells on a polyimide surface was studied. Several IPS cells which have different concentrations of cyano liquid crystals (LCs) were fabricated. We found that the VHR of the IPS cell was decreased with increasing concentration of cyano LCs. Also, the VHR of the IPS cell was increased with increasing specific resistivity of fluorine LCs. The residual DC voltage of the IPS cell by capacitance-voltage (C-V) hysteresis method was decreased with increasing concentration of cyano LCs. The residual DC property of the IPS cell on the rubbed PI surface can be improved by high polarity of cyano LC.

• Journal of IKEEE
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• v.21 no.1
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• pp.7-12
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• 2017

This paper proposed the ESD protection circuit for the high-voltage applications with latch-up immunity and high area efficiency. The proposed circuit has high holding voltage compared to the conventional SCR by inserting the floating regions and applying the segmentation layout. It has the area efficiency is more higher due to the segmentation layout. The proposed circuit has the higher holding voltage of the 21.67V than the 3.39V of the conventional SCR. The electrical characteristics of the proposed circuit was investigated by TCAD simulator, and was proved through the fabrication by using the 0.18 BCD process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.2
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• pp.118-124
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• 1998

This paper describes a relationship of a space vector PWM and a sinusoidal PWM and presents that the space vector PWM can produce linearly the output voltage to the unity MI(modulation index). At first, reference angles and holding angles are derived from expanding a Fourier series of the reference voltage waveform and then the angles are used for the inverter switching to linearize transfer characteristics of the inverter. In addition, the harmonic components of the output voltage are analyzed and on-line control is shown to be feasible by approximating in piecewise-linearization the reference and holding angles versus the MI. In V/f control of the induction motor, it is verified by the experiment that the motor current is changed smoothly for the variation of the inverter input voltage and the change of the reference voltage.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.27-32
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• 2016

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

• Journal of IKEEE
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• v.17 no.3
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• pp.378-384
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• 2013

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.1
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• pp.45-49
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• 1983

The four-layered(metal/insulator/n epi-layer/p+) controlled inversion devices have been fabricated. The I-V curve showed two characteristic states―an On state and an OFF state which were separated by a negative resistance region. The switching voltage and the holding voltage were about 5.0V and 2.5V, respectively. The switching voltage of the device was decreased by photo illumination while the holding voltage remained unaffected.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.69-76
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• 1995

A new device structure has been developed for p-i-n switches. In this structure, the phosphorus-diffused n$^{+}$ layter adjacent to the boron-doped anode is used to short the p$^{+}$ anode-channel(i-region). This change in the anode electrode structure results in a significant improvement in the threshold voltage-to-holding voltage($V_{Th}/V_{h}$) ratio, which is due to the suppression of the hold injection from the anode by the n$^{+}$ layer. The shorted anode p-i-n devices of a 100 .mu.m channel length show an extremely high threshold voltage in the 250~300 V range and a low holding voltage in the 5~9 V range. These features of the device are expected to acdelerate their practical application to power switching circuits.

• Journal of IKEEE
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• v.24 no.3
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• pp.890-894
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• 2020

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.