• Journal of Power Electronics
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• 제16권1호
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.95-98
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• 2006

This paper proposes high speed SRM drive system for blower with a new 4-level inverter and precise excitation position generator. For the high speed blower, a proper inverter and control method are proposed and the output characteristics are analyzed. In order to get a fast build-up and demagnetization of excitation a current, 4-level inverter system is proposed. The proposed 4-level inverter has additional charge capacitor, power switch and diode in the conventional asymmetric converter. The charged high voltage is supplied to the phase winding for fast current build-up, and demagnetization current is charged to additional capacitor of 4-level inverter. In addition, a precise excitation position generator can reduce turn-on and turn-off angle error according to sampling period of digital control system. The proposed high speed SRM drive system is verified by computer simulation and experimental result.

• 한국공작기계학회논문집
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• 제17권6호
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• pp.8-13
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• 2008

At present many research projects on high-speed spindles are being conducted. These projects require a measurement technique which includes heat expansion, vibration and displacement measurement according to angular velocity. This paper presents the development of a measurement system for high-speed spindle displacement. The measurement system is based on $LabView^{(R)}$ and features the following sensors: optical sensor which reacts to the position of a marker on the spindle and enables two Laser Displacement Sensors(LDS). These Laser Displacement Sensors send their data to a DAQ(Data Acquisition Device). It is important that the delay time caused by the response times of the sensors as well as the sampling rate of the DAQ is considered because the spindle revolves at very high speeds.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.110-113
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• 2005

This paper proposes high speed SRM drive system for blower with a new 4-level inverter and precise excitation position generator. For the high speed blower, a proper 12/8 SRM is designed and analyzed. In order to get a fast build-up and demagnetization of excitation a current, now 4-level inverter system is proposed. The proposed 4-level inverter has additional charge capacitor, power switch and diode in the conventional asymmetric converter. The charged high voltage is supplied to the phase winding for fast current build-up, and demagnetization current is charged to additional capacitor of 4-level inverter. In addition, a precise excitation position generator can reduce turn-on and turn-off angle error according to sampling period of digital control system. The proposed high speed SRM drive system is verified by computer simulation.

• 한국컴퓨터정보학회논문지
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• 제5권4호
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• pp.62-68
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• 2000

A/D Board는 Data Acquisition 시스템에서 가장 중요한 하드웨어 기술로써, 컴퓨터를 이용하는 계측기기에 필수적으로 사용되는 장치이다. 특히, 초음파 탐상 장치의 A/D Board는 수 MHz대의 초음파를 디지털로 변환하기 위해 고속의 A/D 변환기가 필요하고, PC 메모리로 직접 전송할 수 있는 DMA 방식의 회로 설계가 요구된다. 본 연구는 측정하려는 대상으로부터 반사된 초음파 신호를 고속의 A/D 변환기에 의해 디지털화 한 후, 데이터의 Peak값을 추출하여 ISA Bus를 통해서 PC로 전송 지켜주는 카드를 설계하였다. 초음파 탐상에 사용되는 주파수가 보통 10MHz 이상이므로 이 신호를 안정적으로 획득하기 위해서는 샘플링 속도가 초음파 주파수 보다 굇배 이상 빨라야 한다. 따라서 50MHz의 샘플링 속도와 8 비트의 분해능을 갖는 A/D 변환기를 사용하였으며, 변환된 초음파 신호를 고속 처리하기 위해 Positive와 Negative Peak Detection 모드를 동시에 동작하도록 VHDL을 이용하여 설계하였다.

• ETRI Journal
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• 제46권2호
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• 전자공학회논문지S
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• 제34S권6호
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• pp.67-76
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• 1997

In radar signal processing, an A/D converter with sufficient dynamic range and high sampling speed is required to detect the weakest target signals in heavy clutter and ECM environments. As the sampling frequency increases, the amount of digital data transfered to the signal processing module is also increased. To overcome these massive data transfer burden, we need an A/D conversion module with an enough data transfer rate. In this paper, we proposed an implementation scheme of a new A/D conversio module that can be used in multi-mode 3-D phased array radar signal processing system, and evaluated the performance. The proposed A/D conversion module is implemented with a standard A/D converter and a 6U-standard VME bus.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1241-1246
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• 2005

본 장은 100MHz 수준의 고속 신호 샘플링을 위해 글리치 최소화 기법을 적용한 8비트 100MHz CMOS D/A 변환기 (Digital - to - Analog Converter : DAC) 회로를 제안한다. 제안하는 DAC는 0.35um Hynix CMOS 공정을 사용하여 설계 및 레이아웃을 하였으며, 응용되는 시스템의 속도, 해상도 및 면적 등의 사양을 고려하여 전류 모드 구조로 적용되었다. D/A 변환기의 선형 특성은 원래의 Spec. 과 유사하였으며, ${\pm}0.09LSB$ 정도의 DNL과 INL오차가 측정되었다. 제작된 칩 테스트 결과에 대한 오동작의 원인을 분석하였으며, 이를 통하여 칩 테스트를 위한 고려사항 등을 제안하였다.

• 전자공학회논문지 IE
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• 제43권3호
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• pp.6-12
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• 2006

이 논문은 100MHz 수준의 고속 신호 샘플링을 위해 글리치 최소화 기법을 적용한 8비트 100MHz CMOS D/A 변환기 (Digital to Analog Converter : DAC) 회로를 제안한다. 제안하는 DAC는 $0.35{\mu}m$ Hynix CMOS 공정을 사용하여 설계 및 레이아웃을 하였으며, 응용되는 시스템의 속도, 해상도 및 면적 등의 사양을 고려하여 전류 모드 구조로 적용되었다. D/A 변환기의 선형 특성은 설계한 Spec. 과 유사하였으며, $\pm$0.09LSB 정도의 DNL과 INL 오차가 측정되었다. 제작된 칩 테스트 결과에 대한 오동작의 원인을 분석하였으며, 이를 통하여 칩 테스트를 위한 고려사항 등을 제안하였다.