Browse > Article
http://dx.doi.org/10.6113/JPE.2016.16.1.227

Digitally Current Controlled DC-DC Switching Converters Using an Adjacent Cycle Sampling Strategy  

Wei, Tingcun (School of Computer Science and Engineering, Northwestern Polytechnical University)
Wang, Yulin (School of Computer Science and Engineering, Northwestern Polytechnical University)
Li, Feng (School of Computer Science and Engineering, Northwestern Polytechnical University)
Chen, Nan (School of Computer Science and Engineering, Northwestern Polytechnical University)
Wang, Jia (School of Computer Science and Engineering, Northwestern Polytechnical University)
Publication Information
Journal of Power Electronics / v.16, no.1, 2016 , pp. 227-237 More about this Journal
Abstract
A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.
Keywords
Adjacent Cycle Sampling (ACS); Digitally controlled DC-DC switching converter; Digital current control algorithm; Digital Slope Compensation (DSC); Sub-harmonic oscillation; Transient response speed;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 S. Chunlei, B. C. Walker, E. Zeisel, B. Hu, and G. H. McAllister, "A Highly Integrated Power Management IC for Advanced Mobile Applications," IEEE Custom Integrated Circuits Conf.(CICC), pp. 85-88, Sep. 2006.
2 B. Sahu and G. A. Rincon-Mora, "A high-efficiency, dual-mode, dynamic, buck-boost power supply IC for portable applications," in 18th Int. Conf. VLSI Design, pp. 858-861, Jan. 2005.
3 Z. Tao, X. Jianping, B, and B. Francois, "Analog-to-digital converter architectures for digital controller of high-frequency power converters," in 32nd Annual Conf. Industrial Electronics(IECON), pp. 2471-2476, Nov. 2006.
4 A. Prodic, D. Maksimovic, and R. W. Erickson, "Design and implementation of a digital PWM controller for a high-frequency switching DC-DC power converter," in 27th Annual Conf. of the Industrial Electronics Society, Vol. 2, pp. 893-898, Nov./Dec. 2001.
5 G. Zhou, J. Xu, C. Mi, and Y. Jin, "Effects of modulations on the sub-harmonic oscillations of digital peak current and digital valley current controlled switching DC-DC converters," in IEEE. 6th Int. Power Electronics and Motion Control Conf.(IPEMC), pp. 1347-1352, May 2009.
6 L. Pengfei, D. Bhatia, X. Lin, and R. Bashirullah, “A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization,” IEEE J. Solid-State Circuits, Vol. 46, No. 9, pp. 2108-2119, Sep. 2011.   DOI
7 M. S. Manoharan, A. Ahmed, and J.-H. Park, “Peak-Valley Current Mode Controlled H-BridgeInverter with Digital Slope Compensation for Cycle-by-Cycle Current Regulation,” Journal of Electrical Engineering and Technology, Vol. 10, No. 5, pp. 709-718, Oct. 2015.   DOI
8 H. Siyu and R. M. Nelms, "Comparison of three implementations of digital average current control for DC-DC converters," in IEEE 40th Annual Conf. Industrial Electronics Society(IECON), pp. 1337-1342, Oct./Nov. 2014.
9 G. Zhou, J. Xu, J. Wang, and Q. Mu, "Improved digital average current control of buck converter with dual-edge modulation," in Int. Conf. Communications, Circuits and Systems(ICCCAS), pp.1309-1313, May 2008.
10 F. Kurokawa and K. Kajiwara, "A novel fast average current mode digital control for DC-DC converter," in IEEE 9th Int. Conf. Power Electronics and Drive Systems(PEDS), pp.1143-1148, Dec. 2011.
11 G. Zhou and J. Xu, “Digital Average Current Controlled Switching DC–DC Converters With Single-Edge Modulation,” IEEE Trans. Power Electron., Vol. 25, No. 3, pp.786-793, Mar. 2010.   DOI
12 M. Aime, G. Gateau, and T. A. Meynard, “Implementation of a peak current control algorithm within a field programmable gate array,” IEEE Trans. Ind. Electron., Vol. 54, No. 1, pp. 406-418, Feb. 2007.   DOI
13 M. Ferdowsi, "An estimative current mode controller for DC-DC converters operating in continuous conduction mode," in Proc. IEEE Appl. Power Electron. Conf., pp. 4, Mar. 2006.
14 G. Zhou, J. Xu, Y. Jin, and W. Wang, "Transient performance comparison on digital peak current controlled switching dc-dc converters in DCM with different digital pulse-width modulations," in IEEE 6th Int. Conf. Power Electronics and Motion Control(IPEMC), pp. 315-319, May 2009.
15 S. Bibian and J. Hua, “Time delay compensation of digital control for DC switch mode power supplies using prediction techniques,” IEEE Trans. Power Electron., Vol. 15, No. 5, pp. 835-842, Sep. 2000.   DOI
16 J. Chen, A. Prodic, R. W. Erickson, and D. Maksimovic, “Predictive digital current programmed control,” IEEE Trans. Power Electron., Vol. 18, No. 1, pp. 411-419, Jan. 2003.   DOI
17 A. Ehrhart, B. Wicht, M. Lin, Y.-S. Huang, L. Yuhuei, and C. Kehorng, "Adaptive pulse skipping and adaptive compensation capacitance techniques in current-mode buck-boost DC-DC converters for fasttransient response," in IEEE 10th Int. Conf. Power Electronics and Drive Systems(PEDS), pp. 373-378, Apr. 2013.
18 C. Lin and W.-H. Ki, "A circuit-oriented geometrical approach in predicting subharmonic oscillation of dc-dc converters with voltage-mode control," in IEEE Int. Symp. Circuits and Systems(ISCAS), pp. 962-965, Jun. 2014.
19 M. Hallworth and S. A. Shirsavar, “Microcontroller-Based Peak Current Mode Control Using Digital Slope Compensation,” IEEE Trans. Power Electron., Vol. 27, No. 7, pp. 3340-3351, Jul. 2012.   DOI
20 T. Grote, F. Schafmeister, H. Figge, N. Frohleke, P. Ide, and J. Bocker, "Adaptive digital slope compensation for peak current mode control," in IEEE Energy Conversion Congress and Exposition(ECCE). pp. 3523-3529, Sep. 2009.