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8bit 100MHz DAC design for high speed sampling  

Lee, Hun-Ki (SELOCO, Inc.)
Choi, Kyu-Hoon (Dept. of Medical Equipment Information, VISION College of Jeonju)
Publication Information
전자공학회논문지 IE / v.43, no.3, 2006 , pp. 6-12 More about this Journal
Abstract
This paper described an 8bit, 100Msample/s CMOS D/A converter using a glitch-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in $0.35{\mu}m$ Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification and the prototype error between DNL and INL is less than $\pm$0.09LSB respectively. Also, the manufactured DAC chip was analyzed the cause of error operation and proposed the field considerations for chip test.
Keywords
CMOS DAC; glitch-time minimization; Current mode; DNL; INL;
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