• Title/Summary/Keyword: High frequency communications

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A 0.13 ${\mu}m$ CMOS UWB RF Transmitter with an On-Chip T/R Switch

  • Kim, Chang-Wan;Duong, Quoc-Hoang;Lee, Seung-Sik;Lee, Sang-Gug
    • ETRI Journal
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    • v.30 no.4
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    • pp.526-534
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    • 2008
  • This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

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Noise-Resistant Visible Light Communications Using Subpulse-VPPM (Subpulse-VPPM 변조를 이용한 잡음에 강한 가시광통신)

  • Kim, Jonghun;Lee, Seungwoo;Ju, MinChul;Park, Youngil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.2
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    • pp.385-389
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    • 2015
  • If visible light communication is to be used against large background noise in indoor environment, low frequency noise should be avoided. To maintain the advantages of LED lighting while transmitting signals, LEDs should be dimmable and free from flickering effect. In this paper, the spectrum of transmission signal is shifted toward high frequency for this purpose. Specifically, we propose a subpulse-VPPM scheme, which can be designed using only digital components, and we implement a test-bed for performance measurement.

The Data Compression Method for increase of Efficiency in Tactical Data Communication over Legacy Radios (Legacy Radio 기반의 전술데이터 통신 효율성 향상 위한 데이터 압축 기법)

  • Sim, Dong-Sub;Shin, Ung-Hee;Kim, Ki-Hyung
    • Journal of the Korea Institute of Military Science and Technology
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    • v.13 no.4
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    • pp.577-585
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    • 2010
  • The Military Tactical Communication technology for effective network-centric warfare is developing. Targeting broadband wireless transmission, core technology for connection, and Transmission technology that secure survivability under High-speed Movement environment. On the one hand, Tactical data communication system that reflects military characteristic is developing on the base of Legacy communication equipment which is used in the field. Because almost every military units in the field have used voice to communicate which lower efficiency of operation, they have made effort to Substitute voice communication which delays military Operation Tempo to digital communication. The Communications environment of troops in Forward edge of battle field area is very poor. Especially in terms of limited frequency allocation and bandwidth. Therefore, improving the efficiency of frequency is essential for Military Tactical Communication. This paper is about The Data Compression Method for increase of Efficiency in Tactical Data Communication over Legacy Radios which are UHF, VHF, HF Radio. I proposed and proved the most efficient Data Compression Method that reflects military characteristic, after analyzing the experimentation, which simulate CAS(Close Air Support mission) data transmission between Pilot and TACP.

Wireless Communication at 310 GHz using GaAs High-Electron-Mobility Transistors for Detection

  • Blin, Stephane;Tohme, Lucie;Coquillat, Dominique;Horiguchi, Shogo;Minamikata, Yusuke;Hisatake, Shintaro;Nouvel, Philippe;Cohen, Thomas;Penarier, Annick;Cano, Fabrice;Varani, Luca;Knap, Wojciech;Nagatsuma, Tadao
    • Journal of Communications and Networks
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    • v.15 no.6
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    • pp.559-568
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    • 2013
  • We report on the first error-free terahertz (THz) wireless communication at 0.310 THz for data rates up to 8.2 Gbps using a 18-GHz-bandwidth GaAs/AlGaAs field-effect transistor as a detector. This result demonstrates that low-cost commercially-available plasma-wave transistors whose cut-off frequency is far below THz frequencies can be employed in THz communication. Wireless communication over 50 cm is presented at 1.4 Gbps using a uni-travelling-carrier photodiode as a source. Transistor integration is detailed, as it is essential to avoid any deleterious signals that would prevent successful communication. We observed an improvement of the bit error rate with increasing input THz power, followed by a degradation at high input power. Such a degradation appears at lower powers if the photodiode bias is smaller. Higher-data-rate communication is demonstrated using a frequency-multiplied source thanks to higher output power. Bit-error-rate measurements at data rates up to 10 Gbps are performed for different input THz powers. As expected, bit error rates degrade as data rate increases. However, degraded communication is observed at some specific data rates. This effect is probably due to deleterious cavity effects and/or impedance mismatches. Using such a system, realtime uncompressed high-definition video signal is successfully and robustly transmitted.

A 3 Stage MMIC Low Noise Amplifier for the Ka Band Satellite Communications and BWLL System (Ka 대역 위성통신 및 BWLL 시스템용 3단 MMIC 저잡음 증폭기 설계 및 제작)

  • 염인복;정진철;이성팔
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.1
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    • pp.71-76
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    • 2001
  • A Ka Band 3-stage MMIC (Monolithic Microwave Integrated Circuits) LNA (Low Noise Amplifiers) has been designed and fabricated far the Ka band satellite communications and BWLL(Broad Band Wireless Local Loop)system. The MMIC LNA consists of two single-ended type amplification stages and one balanced type amplification stage to satisfy noise figure, high gain and amplitude linearity. The 0.15${\mu}{\textrm}{m}$ pHEMT has been used to provide a ultra low noise figure and high gain amplification. Series and Shunt feedback circuits and λ/4 short lines were inserted to ensure high stability over the frequency range form DC to 80 GHz. The size of the MMIC LNA is 3.1mm$\times$2.4mm(7.44mm$^2$). The on wafer measured performance of the MMIC LNA, which agreed with the designed performance, showed the noise figure of less than 2.0 dB, and the gain of more than 26 dB, over frequency ranges from 22 GHz to 30 GHz.

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Performance Evaluation of Turbo coded Adaptive QAM Systems for High-speed Mobile Multimedia Communications (고속 이동 멀티미디어 통신을 위한 터보 부호 적응 QAM 시스템의 성능 분석)

  • 백흥현;정연호
    • Journal of the Institute of Convergence Signal Processing
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    • v.5 no.3
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    • pp.216-222
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    • 2004
  • Frequency selective fading is a limiting factor for transmission rate and performance in high-speed multimedia communications. In this paper, we propose a turbo coded adaptive quadrature amplitude modulation (QAM) system for efficient high-speed transmission. By making use of a user-friendly simulation platform of SPW, the proposed turbo coded adaptive QAM system(TuAQAM) is developed and its performance is evaluated in terms of throughput and BER performance. Two channel models having delay spreads of 700ns and 1400ns are created for the simulations. It is shown that the proposed TuAQAM system provides a performance improvement of approximately 3dB and improved throughput for the channel model whose delay spread is 700ns. Similarly, a performance improvement is also achieved for the channel model whose delay spread is 1400ns.

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High-Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

  • Ryu, Namsik;Jung, Jae-Ho;Jeong, Yongchae
    • ETRI Journal
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    • v.34 no.6
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    • pp.885-891
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    • 2012
  • This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

Resource Allocation Scheme for Public Safety Communications with High-Power User Equipment (재난안전통신 환경에서 고출력 단말의 자원할당 기법)

  • Nam, Jong-Hyun;Shin, Oh-Soon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.2
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    • pp.9-15
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    • 2017
  • In this paper, we propose a resource allocation scheme for high-power user equipment (HPUE) in public safety communication environments. The use of HPUE is being considered to increase the throughput and communication range of a UE in the disaster area where normal communication links are not available. However, HPUE may cause higher interference to UE's in adjacent cells that are allocated to the same radio resources. Therefore, it is necessary to deal with the potential interference through frequency planning and resource allocation. The performance of the proposed resource allocation scheme is evaluated through simulations in 3GPP public safety communication scenarios.

A RFI Cancellation Technique for DMT-based VDSL Systems (DMT 기반의 VDSL 시스템을 위한 RFI 감쇄기법)

  • 정만영;조용수;백종호;유영환;송형규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.1A
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    • pp.156-166
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    • 2000
  • In discrete multi-tone (DMT)-based very high bit-rate digital subscriber line (VDSL) systems, the ingressed RFI (Radio Frequency Interference) accompanied by transmitted signal at the receiver is known to cause the spectralleakage by the finite-point FFT, resulting in significant performance degradation.0 this paper, we propose a RFIcancellation technique which can compensate the ingressed RFI efficiently, especially for a high data-rate VDSLsystem. The proposed technique compensates the performance degradation of e VDSL system due to RFI byusing a time-domain RFI canceller whose coefficients are obtained from the estimated center frequency of RFI inthe frequency domain under the assumption that the ingressed RFI is a narrow-band signal compared to VDSLsampling frequency. The proposed technique requires no training symbol and convergence period, and worksproperly even when spectral shape of the ingressed RFI is unknown or arbitrary. Feasibility of the proposedtechnique is demonstrated via a computer simulation by comparing its performance with the performance of theprevious RFI cancellation technique.

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A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 ㎛ BCD

  • Kim, Hongjin;Park, Young-Jun;Park, Ju-Hyun;Ryu, Ho-Cheol;Pu, Young-Gun;Lee, Minjae;Hwang, Keumcheol;Yang, Younggoo;Lee, Kang-Yoon
    • Journal of Power Electronics
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    • v.16 no.6
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    • pp.2024-2034
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    • 2016
  • This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.