• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1650-1658
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• 2018

Multilevel converters are being widely used in medium-voltage high-power applications including motor drive systems, utility power transmission, and distribution systems. Selective harmonic elimination (SHE) is a well-known modulation method to generate high quality output voltage waveforms. This paper presents a new simple practical method for generating a generalized five-level waveform without selected low order harmonics. This method is based on a phase-shifted expression for the SHE problem, which can analytically calculate the exact values of switching angles and the feasible modulation index range for three-level and five-level waveforms. The proposed method automatically determines the number of transitions between levels and generates proper output waveform without solving complex trigonometric equations. Due to the simplicity of the computational burden, the real-time implementation of the proposed algorithm can be performed by a simple processor. Simulation and experiment results verify the correctness and effectiveness of the proposed method.

• Journal of Power Electronics
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• v.16 no.2
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• pp.480-489
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• 2016

A novel hybrid carrier-based pulse width modulation (CBPWM) scheme that combines unipolar and dipolar modulations is proposed for single-phase three-level rectifiers, which are widely applied in railway traction drive systems. The proposed CBPWM method can satisfy the volt-second balancing principle in the complete modulation index region through overmodulation compensation. The modulation scheme features two modulation modes: unipolar and dipolar. The operation range limits of these modulation modes can be modified by changing the separation coefficient. In comparison with the traditional unipolar CBPWM, the proposed hybrid CBPWM scheme can provide advantageous features, such as lower high-order harmonic distortion of the line current and better utilization of switching frequency. The separation coefficient value is optimized to achieve the maximum utilization of these advantages. The experimental results verify the feasibility and effectiveness of the proposed hybrid CBPWM scheme.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.75-81
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• 2020

We introduce a new visible light communication (VLC) method in which three-level return-to-zero (RZ) modulation is used for flicker-free transmission. In the VLC transmitter, the three-level RZ modulation ensures that the average optical power is constant; thus, a flicker-free light-emitting diode (LED) light is achieved. In the VLC receiver, a resistor-capacitor high-pass filter is used for generating spike signals, which are used for data recovery while eliminating the 120 Hz optical noise from adjacent lighting lamps. In transmission experiments, we applied this method for wireless transmission of an air quality sensor message using the visible light of an LED array. This configuration is useful for the construction of indoor wireless sensor networks for air pollution monitoring using LED lights.

• ETRI Journal
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• v.45 no.6
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• pp.974-981
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• 2023

This paper presents a transition-limited pulse-amplitude modulation (TLPAM) signaling method to enable a high data rate and robust wireline communications. TLPAM signaling addresses the impact of high intersymbol interference (ISI) ratios in conventional M-ary PAM signaling methods by limiting the maximum voltage transition level between adjacent symbols. The implementation of a TLPAM signaling encoder is realized by setting back the most significant bits (MSBs) in the queue. The correlation between TLPAM's maximum transition level, effective data rate, and eye width/height is analyzed with various channel loss parameters, followed by characterization and measurement results with a realistic channel setup. The analysis and experimental results reveal the effectiveness of the proposed TLPAM signaling scheme for achieving a high data rate with minimal interference.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.347-350
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• 2000

This paper deals with the novel DPWM(discontinuous PWM) for 3-level inverter. Although DPWM methods generate higher harmonics than SVPWM they are of special interest because of their lower switching losses. And in the high modulation region the harmonic characteristics of DPWM is superior to the that of CPWM. However when DPWM applies to the 3-level inverter there is the problem that the output state is varied suddenly in the low modulation region($\textrm{m}_{I}$=0~0.5) The novel DPWM that this problem improves will be introduced.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of Power Electronics
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• v.17 no.1
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• pp.127-135
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• 2017

Recently the researches on modular multi-level converter (MMC) are being highlighted because high quality and efficient power transmission have become key issues in high voltage direct current (HVDC) systems. This paper proposes an improved pre-charging method for the sub-module (SM) capacitor of MMC-based HVDC systems, which operates in the nearest level control (NLC) modulation and does not need additional circuits or pulse width modulation (PWM) techniques. The feasibility of the proposed method was verified through computer simulations for a scaled 3-phase 10kVA MMC with 12 SMs per each arm. Hardware experiments with a scaled prototype have also been performed in the lab to confirm the simulation results.

• Journal of Power Electronics
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• v.19 no.4
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• pp.944-955
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• 2019

In this paper, the three-level T-type neutral-point-clamped indirect matrix converter topology and the relative space vector modulation methods are introduced to improve the voltage transfer ratio and output voltage performance. The presented converter topology is based on combinations of cascaded-rectifier and three-level T-type neutral-point-clamp inverter. It can overcome the limitation of voltage transfer ratio of the conventional matrix converter and the high voltage rating of power switches of conventional matrix converter. Two SVPWM strategies for proposed converter are described in this paper to achieve the advantages features such as: sinusoidal input/output currents and three-level output voltage waveforms. Results from Psim 9.0 software simulation are provided to confirm the theoretical analysis. Hence, a laboratory prototype was implemented, and the experimental results are shown to validate the simulation results and to verify the effectiveness of the proposed topology and modulation strategies.