• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Korean Chemical Engineering Research
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• v.60 no.2
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• pp.313-319
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• 2022

AlGaN/GaN based HfO₂ MOSHEMT (metal oxide semiconductor high electron transistor) with different gate recess depth was simulate to demonstrate a successful normally-off operation of the transistor. Three types of the HEMT structures including a conventional HEMT, a gate-recessed HEMT with 3 nm thick AlGaN layer, and MIS-HEMT without AlGaN layer in the gate region. The conventional HEMT showed a normally-on characteristics with a drain current of 0.35 A at V_G = 0 V and V_DS = 15 V. The recessed HEMT with 3 nm AlGaN layer exhibited a decreased drain current of 0.15 A under the same bias condition due to the decrease of electron concentration in 2DEG (2-dimensional electron gas) channel. For the last HEMT structure, distinctive normally- off behavior of the transistor was observed, and the turn-on voltage was shifted to 0 V.

• Journal of the Korean Ceramic Society
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• v.22 no.6
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• pp.37-41
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• 1985

Several $Al_2O_3$-based polycrystalline which had different dopant ratio in the range of 0.5mol% were prepared by doping pure $Cr_2O_3$, $ZrO_2$, $HfO_3$ Single crystalline which had same composition with above polycrystalline were made by means of floating zone method. This study examined the role of each dopant for enhancing the mefchanical properties of $Al_2O_3$-based Ceramics. Optical micrographs $({\times}200)$ of $Al_2O_3-Cr_2O_3$ single crystal showing not only radial crack (rc) on the specimen surface but median crack (mc) and lateral crack (lc) under surface at the edge of indentation mark. Fracture toughness of $Al_2O_3$-based Ceramics was increased with $ZrO_2$ content. Alloying effect of $Cr_2O_3$ contributed to the hardness of $Al_2O_3$ based ceramics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.269.1-269.1
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• 2009

• Journal of the Korean Ceramic Society
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• v.21 no.4
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• pp.327-332
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• 1984

Proper amount of $Al_2O_3$ must be added to increase the yield of mullite which is formed from free silica decomposed from kaolin. The previous study has suggested that Al powder may be a good $Al_2O_3$ supply source at 1400~150$0^{\circ}C$. In this study the application of Al powder is discussed about its mullitization behavior in the higher temperature range of 1500~175$0^{\circ}C$ the results of which compared with those obtained from the reactive $Al_2O_3$ and activated $Al_2O_3$. The oxdation and reaction stages of Al powder were analyzed by DTA crystal growth andmorphology of the mullite were observed by SEM and the yields of the mullite were compared according to their solubilities in HF solution.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.279-279
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• 2011

나노 입자를 이용한 비휘발성 메모리 소자의 전기적 특성 향상을 위하여 일함수가 Si 보다 큰 금속, 금속산화물, 금속 실리사이드 나노입자를 이용한 다양한 형태의 메모리 구조가 제안되어져 왔다.[1] 특히 이와 같은 나노 부유 게이트 구조에서 터널 절연막의 구조를 소자의 동작 속도를 결정하는데 이는 터널링 되어 주입되는 전자의 확률에 의존하기 때문이다. 양자 우물에 국한된 전하가 누설되지 않으면서 주입되는 전자의 터널링 확률을 증가시키기 위하여, dielectric constant 와 barrier height를 고려한 다양한 구조의 터널 절연막의 형태가 제안 되었다.[2-3] 특히 낮은 전계에서도 높은 터널링 확률은 메모리 소자의 동작 속도를 향상시킬 수 있다. 본 연구에서는 n형 Si 기판위에 Si3N4 및 HfAlO를 각각 1.5 nm 및 3 nm 로 atomic layer deposition 방법으로 증착하였으며 3~5 nm 지름을 가지는 $TiSi_2$ 및 $WSi_2$ 나노 입자를 형성한 후 컨트롤 절연막인 $SiO_2$를 ultra-high vacuum sputtering을 사용하여 20 nm 두께로 형성 하였다. 마지막으로 $200{\mu}m$ 지름을 가지는 Al 전극을 200 nm 두께로 형성하여 나노 부유 게이트 커패시터를 제작하였다. 제작된 소자는 Agilent E4980A precision LCR meter 및 HP 4156A precision semiconductor parameter analyzer 를 사용하여 전기용량-전압 및 전류-전압 특성분석을 하여 전하저장 특성 및 제작된 소자의 터널링 특성을 확인 하여 본 연구를 통하여 제작된 나노 부유 게이트 커패시터 구조가 메모리 소자응용이 가능함을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.186-186
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• 2010

소자의 축소화에 따라 floating gate 형의 flash 메모리 소자는 얇은 게이트 절연막 등의 이유로, 이웃 셀 간의 커플링 및 게이트 누설 전류와 같은 문제점을 지니고 있다. 이러한 문제점을 극복하기 위해 charge trap flash 메모리 (CTF) 소자가 연구되고 있지만, CTF 메모리 소자는 쓰기/지우기 속도와 데이터 보존 성능간의 trade-off 관계와 같은 문제점을 지니고 있다. 최근, 이를 극복하기 위한 방안으로, 다른 유전율을 갖는 유전체들을 적층시킨 터널 절연막을 이용한 Tunnel Barrier Engineered (TBE) 기술이 주목 받고 있다. 따라서, 본 논문에서는 TBE 기술을 적용한 MIS-capacitor를 높은 유전율을 가지는 Al2O3와 HfO2를 이용하여 제작하였다. 이를 위해 먼저 Si 기판 위에 Al2O3 /HfO2 /Al2O3 (AHA)를 Atomic Layer Deposition (ALD) 방법으로 약 2/1/3 nm의 두께를 가지도록 증착 하였고, Aluminum을 150 nm 증착 하여 게이트 전극으로 이용하였다. Capacitance-Voltage와 Current-Voltage 특성을 측정, 분석함으로써, AHA 구조를 가지는 터널 절연막의 전기적인 특성을 확인 하였다. 또한, high-k 물질을 이용한 터널 절연막을 급속 열처리 공정 (Rapid Thermal Annealing-RTA) 과 H2/N2분위기에서 후속열처리 공정 (Post-RTA)을 통하여 전기적인 특성을 개선 시켰다. 적층된 터널 절연막은 열처리를 통해 터널링 전류의 민감도의 향상과 함께 누설전류가 감소됨으로서 우수한 전기적인 특성이 나타남을 확인하였으며, 적층된 터널 절연막 구조와 적절한 열처리를 이용하여 빠른 쓰기/지우기 속도와 전기적인 특성이 향상된 비휘발성 메모리 소자를 기대할 수 있다.

• Korean Journal of Mineralogy and Petrology
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• v.36 no.3
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• pp.185-197
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• 2023

The Gubong Au-Ag deposit consists of eight lens-shaped quartz veins. These veins have filled fractures along fault zones within Precambrian metasedimentary rock. This has been one of the largest deposits in Korea, and is geologically a mix of orogenic-type and intrusion-related types. Korea Mining Promotion Corporation drilled into a quartz vein (referred to as the No. 6 vein) with a width of 0.9 m and a grade of 27.9 g/t Au at a depth of -728 ML by drilling (No. 90-12) in the southern site of the deposit, To further investigate the potential redevelopment of the No. 6 vein, another drilling (No. 04-1) was carried out in 2004. In 2004, samples (wallrock, wallrock alteration and quartz vein) were collected from the No. 04-1 drilling core site to study the occurrence and chemical composition of Ti-bearing minerals (ilmenite, rutile). Rutile from mineralized zone at a depth of -275 ML occur minerals including K-feldspar, biotite, quartz, calcite, chlorite, pyrite in wallrock alteration zone. Ilmenite and rutile from ore vein (No. 6 vein) at a depth of -779 ML occur minerals including white mica, chlorite, apatite, zircon, quartz, calcite, pyrrhotite, pyrite in wallrock alteration zone and quartz vein. Based on mineral assemblage, rutile was formed by hydrothermal alteration (chloritization) of Ti-rich biotite in the wallrock. Chemical composition of ilmenite has maximum values of 0.09 wt.% (HfO₂), 0.39 wt.% (V₂O₃) and 0.54 wt.% (BaO). Comparing the chemical composition of rutile at a depth -275 ML and -779 ML, Rutile at a depth of -779 ML is higher contents (WO₃, FeO and BaO) than rutile at a depth of -275 ML. The substitutions of rutile at a depth of -275 ML and -779 ML are as followed : rutile at a depth of -275 ML Ba²⁺ + Al³⁺ + Hf⁴⁺ + (Nb⁵⁺, Ta⁵⁺) ↔ 3Ti⁴⁺ + Fe²⁺, 2V⁴⁺ + (W⁵⁺, Ta⁵⁺, Nb⁵⁺) ↔ 2Ti⁴⁺ + Al³⁺ + (Fe²⁺, Ba²⁺), Al³⁺ + V⁴⁺+ (Nb⁵⁺, Ta⁵⁺) ↔ 2Ti⁴⁺ + 2Fe²⁺, rutile at a depth of -779 ML 2 (Fe²⁺, Ba²⁺) + Al³⁺ + (W⁵⁺, Nb⁵⁺, Ta⁵⁺) ↔ 2Ti⁴⁺ + (V⁴⁺, Hf⁴⁺), Fe²⁺ + Al³⁺ + Hf ⁴⁺ + (W⁵⁺, Nb⁵⁺, Ta⁵⁺) ↔ 2Ti⁴⁺ + V⁴⁺ + Ba²⁺, respectively. Based on these data and chemical composition of rutiles from orogenic-type deposits, rutiles from Gubong deposit was formed in a relatively oxidizing environment than the rutile from orogenictype deposits (Unsan deposit, Kori Kollo deposit, Big Bell deposit, Meguma gold-bearing quartz vein).

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.